Al Burk

Recent progress in SiC DMOSFETs and JBS diodes at Cree

This paper discusses the recent progress in large area silicon carbide (SiC) DMOSFETs and junction barrier Schottky (JBS) diodes. 1.2 kV and 10 kV SiC DMOSFETs have been produced with die areas greater than 0.64 cm2. SiC JBS diode dies also rated at 1.2 kV and 10 kV have been produced with die areas exceeding 1.5 cm2. These results demonstrate that SiC power devices provide a significant leap forward in performance for industrial electronics applications. At 1.2 kV, SiC DMOSFETs offer a reduction of power loss of greater than 50 % with dies less than half the size when compared to silicon (Si) IGBTs. The SiC JBS diodes offer significant reductions in reverse recovery losses. At 10 kV, there are no Si devices that can compete with SiC on a single device basis. Data on 1.2 kV and 10 kV devices are presented along with future trends.

Ultra high voltage (>12 kV), high performance 4H-SiC IGBTs

We present our latest developments in ultra high voltage 4H-SiC IGBTs. A 4H-SiC P-IGBT, with a chip size of 6.7 mm × 6.7 mm and an active area of 0.16 cm2 exhibited a record high blocking voltage of 15 kV, while showing a room temperature differential specific on-resistance of 24 mΩ-cm2 with a gate bias of -20 V. A 4H-SiC N-IGBT with the same area showed a blocking voltage of 12.5 kV, and demonstrated a room temperature differential specific on-resistance of 5.3 mΩ-cm2 with a gate bias of 20 V. Buffer layer design, which includes controlling the doping concentration and the thickness of the field-stop buffer layers, was used to control the charge injection from the backside. Effects on buffer layer design on static characteristics and switching behavior are reported.

High performance, ultra high voltage 4H-SiC IGBTs

We present our latest developments in ultra high voltage 4H-SiC IGBTs. A 4H-SiC P-IGBT, with a chip size of 6.7 mm × 6.7 mm and an active area of 0.16 cm2 exhibited a record high blocking voltage of 15 kV, while showing a room temperature differential specific on-resistance of 24 mΩ-cm2 with a gate bias of -20 V. A 4H-SiC N-IGBT with the same area showed a blocking voltage of 12.5 kV, and demonstrated a room temperature differential specific on-resistance of 5.3 mΩ-cm2 with a gate bias of 20 V. Buffer layer design, which includes controlling the doping concentration and the thickness of the field-stop buffer layers, was used to control the charge injection from the backside. Effects on buffer layer design on static characteristics and switching behavior are reported.

Physical phenomena affecting performance and reliability of 4H–SiC bipolar junction transistors

Abstract The silicon carbide bipolar junction transistor (BJT) is attractive for use in high-voltage switching applications offering high-voltage blocking characteristics, low switching losses, and is capable of operating at current densities exceeding 300xa0A/cm2. However, performance reliability issues such as degradation of current gain and on-resistance currently prohibit commercial production of 4H–SiC BJTs. This paper examines the physical mechanisms responsible for this degradation as well as the impact that these physical phenomena have on device performance. Results were obtained through the examination of several types of N–P–N BJT structures using various fabrication methodologies. Electron-beam induced current (EBIC) and potassium hydroxide (KOH) etching were used to characterize defect content in the material, before and after device current stress, when possible. It was found that Shockley stacking faults (stress-induced structures) associated with the forward voltage drift phenomenon in SiC bipolar diodes, also play a major role in the reduction of gain and an increase of on-resistance of the BJTs. However, results from some devices suggest that additional processes at the device periphery (edge of the emitter) may also contribute to degradation in electrical performance. Hence, it is essential that the sources of electrical degradation, identified in this paper, be eliminated for SiC BJTs to be viable for commercial scale production.

20 kV, 2 cm 2 , 4H-SiC gate turn-off thyristors for advanced pulsed power applications

The development of high-voltage power devices based on wide bandgap semiconductor such as silicon carbide (SiC) has attracted great attention due to its superior material properties over silicon for high-temperature applications. Among the high-voltage SiC power devices, the 4H-SiC gate turn-off thyristor (GTO) offers excellent current handling, very high voltage blocking, and fast turn-off capabilities. The 4H-SiC GTO also exhibits lower forward voltage drop than the IGBT-based switches, resulting in lower losses during normal operation. It is an ideal switch for pulsed power applications that require high turn-on di/dt. In order to achieve a blocking capability of or greater than 20 kV in SiC, a thick drift epi-layer (> 160 μm) with an improved carrier lifetime (5 ~ 10 μs) is necessary to obtain a full conductivity modulation. In this paper, for the first time to our knowledge, we report our recently developed 1×2 cm2, 20 kV, 4H-SiC p-GTO using a 160 μm, 2×1014/cm3 doped, p-type drift layer. The active conducting area of the device is 0.53 cm2. Due to the limitations of the high-voltage test set-up, the 4H-SiC p-GTO showed an on-wafer gate-to-anode blocking voltage of 19.9 kV at a leakage current of 1 μA, which corresponds to a one-dimensional (1D) maximum electrical field of ~ 1.5 MV/cm at room-temperature. To measure this large area, 4H-SiC, p-GTO at high current levels (> 100 A/cm2), the forward characteristics of the device were evaluated using a Tektronix 371 curve tracer in pulse mode. A differential specific on-resistance of 11 MΩ-cm2 was obtained at a gate current of 0.35 A and a high current of 300 A/cm2 ~ 400 A/cm2. More results and discussion will be presented at the conference.

Advanced silicon carbide gate turn-off thyristor for energy conversion and power grid applications

The need for power semiconductor devices capable of high-voltage, high-frequency, and high-temperature operation has been continuously growing, especially for energy conversion system and related power grid applications. However, current power converters built with silicon switches are quite bulky and inefficient, making their utilization difficult in practical energy conversion and power grid systems. The development of high-voltage power devices based on wide bandgap semiconductor such as silicon carbide (SiC) has attracted great attention due to its superior material properties over silicon. Among the high-voltage SiC power devices, SiC gate turn-off thyristor (GTO) offers excellent current handling, very high voltage blocking, and fast turn-off capabilities. SiC GTO also exhibits lower forward voltage drop than the IGBT-based switch, resulting in lower losses during normal operation. In this paper, we report our recently developed 1 × 1 cm2, 12 kV SiC p-type GTO with improved carrier lifetime.

A Comparison of the Microwave Photoconductivity Decay and Open-Circuit Voltage Decay Lifetime Measurement Techniques for Lifetime-Enhanced 4H-SiC Epilayers

This work compares the optical microwave photoconductivity decay (μPCD) and electrical open-circuit voltage decay (OCVD) techniques for measuring the ambipolar carrier lifetime in 4H-silicon carbide (4H-SiC) epitaxial layers. Lifetime measurements were carried out by fabricating P+/intrinsic/N+ (PiN) diodes on 100-μm-thick, 1xa0×xa01014xa0cm−3 to 4.5xa0×xa01014xa0cm−3 doped N-type 4 H-SiC epilayers, and measuring the lifetime optically using μPCD prior to metallization, then electrically using OCVD after contact deposition. Both as-grown epilayers as well as epilayers with improved lifetime (via thermal oxidation) were measured using both techniques. The observed ambipolar lifetime was improved from 1.4xa0μs on an unenhanced wafer to 4xa0μs on a wafer enhanced through the oxidation process as measured by μPCD. Little difference was observed between the μPCD and OCVD measurements on the unenhanced wafer; the ambipolar lifetime on the enhanced wafer measured by OCVD was approximately 5.5xa0μs, or 1.5xa0μs higher than the μPCD measurement. Continuous evaluation of the OCVD transient waveform was necessary due to the high lifetime in the enhanced wafer; shunt resistances included to discharge the P+/N junction capacitance were found to damp the OCVD response and yield low values for the measured lifetime. Simulation of the μPCD measurement including various surface recombination conditions yielded a good match to experimentally observed μPCD measurements for high values of the surface recombination velocity. The OCVD lifetime measurement technique is expected to yield measured lifetime values closer to the physical value due to its independence from surface conditions, provided that the experimental conditions are appropriately chosen.

100 mm GaN-on-SiC RF MMIC technology

100 mm diameter 4H-SiC High Purity Semi-insulating substrates are now being manufactured in high volume. GaN HEMT layers grown on 100 mm SiC substrates have shown excellent sheet resistivity and AlGaN thickness uniformities (σ/mean) of 1.3 and 1.1%, respectively. The fabrication process for MMIC manufacture was adapted to the larger diameter substrates without requiring any change to the process design kits for the foundry. MIM capacitor processes were optimized, and resistor process, wafer thinning and slot via etching were all adapted to the larger platform. These 100 mm wafers are now being used in high volume production of both high power discrete GaN devices, as well as MMICs. Commercially available MMICs have been released to production using this 100 mm platform. A wide band 25 Watt power amplifier is discussed, along with a 3 watt driver capable of DC-4 GHz operation.