Pritam Bhattacharjee

SPICE Modeling and Analysis for Metal Island Ternary QCA Logic Device

The exploration of work ability of the new trend in quantum dot cellular automata (QCA)—the ternary QCA, is the major focus in this paper. Both physically and electrically, our tQCA approach is proving its excellence in comparison to the existing binary QCA (bQCA). We also propose a model description for tQCA that will help in determining its logic performances while operating it in the nano computing regime.

A 90 nm leakage control transistor based clock gating for low power flip flop applications

The continuous growing demand of portable battery-powered electronics devices hunts for Nano-electronic circuit design for ultra-low power applications by reducing dynamic power, static power and short circuit power. In sequential circuit elements of an IC, a notable amount of power dissipation occurs due to the rapid switching of high frequency clock signals, which do not fetch any data bit or information. The needless switching of clock, during the HOLD phase of either ‘logic 1’ or ‘logic 0’, may be abolished using gated clock. In this paper, we have presented a new clock gating technique incorporating Leakage Control Transistor. The improvised technique is employed to trigger a D-Flip Flop using 90nm PTM technology at 1.1V power supply. We have observed an impressive reduction in power, delay and latency using the proposed gating logic, which has outsmarted the existing works. The simulation is also performed in smaller technology nodes such as 65nm, 45nm and 32 nm to notice the change in delay, dynamic power and static power of the circuit.

A Novel Gating Approach to Alleviate Power and Ground Noise in Silicon Chips

As the performing ability of a silicon chip relies on the power supply voltage, it must be configured using genuine power and ground bond pads for mitigating power and ground noise (PGN), which is ...

Variation aware intuitive clock gating to mitigate on-chip power supply noise

ABSTRACT With the advent of semiconductor process technology, both the dynamic and static power consumption have become major concerns for the circuit designers. Though clock gating (CG) is a potentially accomplished technique to minimise the dynamic power, it generally fails to cut down the static power dissipation. To address the same, we have unveiled a new CG scheme incorporating leakage control transistor, which simultaneously curbs the static and dynamic power along with the alleviation of power supply noise (PSN) in silicon chips by smartly controlling the current ramp (di/dt) and average current i(t): the main contributors to PSN. The proposed CG does not only save average, dynamic and static power by 84.34%, 90.33% and 66.73%, respectively, but also reduces PSN by 84.44% with respect to its non-gated counterpart when simulated using Cadence Virtuoso® for 90 nm Generic Process Design Kit at a switching frequency of 5 GHz and power supply voltage of 1.1 V.