Edmund Pierzchala

A field programmable analog array for continuous, fuzzy, and multi-valued logic applications

We propose a novel approach to the realization of continuous, fuzzy, and multi-valued logic (mvl) circuits. We demonstrate how a general-purpose field programmable analog array (FPAA), with cells realizing simple arithmetic operations on signals, can be used for this purpose. The FPAA, which is being implemented in a bipolar transistor array technology, operates from /spl plusmn/3.3 V or /spl plusmn/5 V power supplies and works in the range of frequencies up to several hundred MHz.<<ETX>>

Current-mode amplifier/integrator for a field-programmable analog array

An electronically-programmable analog circuit (EPAC), based on the switched-capacitor (SC) technique, is an analog counterpart of digital FPGAs. The full speed potential of analog circuits, however, can be utilized only by continuous-time (CT) field-programmable analog arrays (FPAAs). In this paper an example of an FPAA structure with local interconnections is shown. Each cell derives a weighted sum of selected signals from four nearest neighbors, and optionally performs integration (ideal or lossy) to produce its own output signal.

Ternary and quaternary lattice diagrams for linearly-independent logic, multiple-valued logic, and analog synthesis

Ternary and quaternary lattice diagrams are introduced that can find applications to submicron design, and designing new fine-grain digital, analog and mixed FPGAs. They expand the ideas of lattice diagrams and linearly-independent (LI) logic. In a regular layout, every cell is connected to 4, 6 or 8 neighbors and to a number of vertical, horizontal and diagonal buses. Various lattices and algorithms for their creation are presented.

A High-Frequency Field-Programmable Analog Array (FPAA) Part 2: Applications

This paper presents a variety of applications of an FPAA based on a regular pattern of signal-processing cells and primarily local signal interconnections. Despite the limitations introduced by local interconnections, the presented architecture accommodates a wide variety of linear and nonlinear circuits found in many signal processing systems. Thus it effectively proves that it is possible to improve the performance of an FPAA by means of constraining the interconnection pattern, without significantly limiting the class of circuits it can implement.

AN EXACT SOLUTION TO THE FITTING PROBLEM IN THE APPLICATION SPECIFIC STATE MACHINE DEVICE

In this paper the fitting problem for a new Application Specific State Machine Device, CY7C361, from Cypress Semiconductor is formulated and the solution is proposed. This fitting problem consists of mapping a netlist obtained from high-level synthesis into the chip’s physical resources. In general, a mapping (fitting) problem can be formulated as one of the labeled graph isomorphism between the netlist graph and the subgraph of the resources graph. However, the specific architecture-related constraints of the CY7C361 device cause the fitting problem to be generalized as a graph isomorphism problem with some additional mapping constraints and node multiplication (placing some nodes of the netlist graph in more than one node of the physical graph). Such formulation is quite general for a class of Complex Programmable Logic Device (CPLD) fitting problems, and has not been found in the literature. We implemented an exact, constraint-based, tree searching algorithm with several kinds of backtracking.

An algorithm and architecture for approximate string matching

Approximate string matching attempts to determine how similar two strings are. An algorithm is developed for determining relative string similarity. An architecture for comparing strings using this algorithm is also developed. Using parallelism and iterative techniques, the similarity value is calculated. The length and number of matching substrings determine the amount of similarity.<<ETX>>

An exact algorithm for the technology fitting problem in the application specific state machine device

The fitting problem for a new application-specific state machine device, CY7C361, from Cypress Semiconductor is formulated, and a solution is proposed. This fitting problem consists of mapping the netlist obtained from high-level synthesis into the chips physical resources. In general, the mapping (fitting) problem can be formulated as one of the labeled graph isomorphism between the netlist graph and the subgraph of the resources graph. However, the specific architecture-related constraints of the CY7C361 device cause the fitting problem to be generalized as a graph isomorphism problem with some additional mapping constraints. The formulation is quite general for a class of electronically programmable logic device (EPLD) fitting problems. An exact, constraint-based, tree searching algorithm with several kinds of backtracking was implemented.<<ETX>>

Low-voltage Gilbert current-gain cell

A modified Gilbert current gain cell works with a single supply voltage as low as 1.5 V (2V/sub BE/) and reduced power consumption. The circuit inherits most features of the original cell, including the ability to be cascaded without increasing the supply voltage. No special technological features are required to implement the circuit. The design has been verified experimentally using CA 3046 and CA 3096 transistor arrays.

Highly linear VHF current-mode Miller integrator with 90 dB DC gain

This paper presents a concept and an implementation of a current-mode integrator based on the Miller effect. The circuit has a highly linear, no feedback, current path, implemented using a Gilbert amplifier cell, and a voltage feedback path with capacitors, realizing integration. A bipolar transistor array process with devices with an f/sub T/ of 8 GHz has been used for the circuit simulation. Phase response of -90/spl plusmn/0.5/spl deg/ has been obtained in the frequency range of 1 MHz to 670 MHz (the low-frequency pole can be tuned electronically down to about 3 Hz). Excess phase can be compensated electronically to obtain exactly -90/spl deg/ for any frequency in the entire useful range. The gain of the circuit can be tuned electronically over at least 40 dB. THD for 1 MHz is better than 0.052% for an output current of 2.8 mA/sub pp/, which represents 93% of the output tail current. DC gain of the circuit can be turned up to over 90 dB.

Knowledge based extension of DIADES system for the analysis and synthesis of TGC circuits

A new and uniform approach to the computer-aided analysis and synthesis of analog circuits is presented. The system is specialized for transconductance-grounded capacitance circuits (TGC). The analysis is a transformation from a signal flow graph (SFG) to a transfer function (TF). It is based on a step-by-step transformation from SFG to TF by reductions of nodes: summation, multiplication, and feedback. Symbol manipulation of multivariate rational functions is used. The synthesis is a process of transforming a LC-ladder filter SFG to a TGC circuit. Heuristic synthesis procedures, inverse to the ones used in the analysis, search the solution space of equivalent SFGs and are theoretically able to find the optimal solution. The synthesis method includes three stages: SFG labeling, synthesis of the SFG branch transfer functions, and SFG repolarization. The application of some synthesis rules is illustrated on examples.<<ETX>>