Alan Lucero

Define electrical packing temperature cycling requirement with field measured user behavior data

In this paper, a user behavior based solder joint reliability modeling approach has been proposed to estimate the design and test requirements for the second level interconnect (SLI) reliability prediction. This approach uses a numerical tool to integrate solder joint creep damage during the actual use condition that was collected from a large user sample size. The resultant damage per time period was then input to the solder joint fatigue model to estimate equivalent damage to testing duration. The is a physics based approach and is expected to provide more accurate product life prediction and reliability performance demand for BGA package designs.

Setting use conditions for reliability modeling

Use conditions (UCs) are necessary inputs for knowledge-based qualification reliability modeling calculations, and are implied by standard-based qualification stress conditions. We describe a method for setting CPU UCs. A sampled distribution of field data is analyzed, accounting for the reliability model Weibull shape factor. That is combined with other information to determine a reference value for modeling, with appropriate conservatism. We present application to notebook PCs for both silicon and thermo-mechanical CPU wearout mechanisms.

A preliminary solder joint life prediction model by experiment and simulation for translation of use condition to temperature cycling test condition

This paper introduces a new preliminary solder joint fatigue model based on thermo-mechanical finite element analysis (FEA) simulation results and the use of extensive solder joint reliability (SJR) experimental data for ball grid array (BGA) packages. A comprehensive FEA modeling method for temperature cycling (TC) loading was defined based on thorough and detailed convergence studies on modeling approaches, mesh sensitivities, analysis parameters, material parameters, boundary conditions and thermal loading conditions. Extensive reliability data was collected for various package designs, form factors, board thicknesses and testing conditions to demonstrate feasibility. The result is a solder joint fatigue model derived from FEA thermal mechanical modeling results and empirical reliability data regression fitting. Next, this FEA modeling method was coupled with a transient heat transfer method to integrate thermal gradients that exist in actual product use condition (UC) duty cycles. A new UC method is demonstrated based on a common physical damage metric calculated from numerical simulations for UC (with real user behavior data and temperature gradient) and TC (uniform temperature) conditions. The derived SJR fatigue model was combined with the newly developed UC method to establish new TC test requirements based on the actual use condition duty cycling.

Comparison of thin film cracking and delamination for aluminum and copper silicon interconnects with organic packaging

Silicon passivation cracking and interconnect metal thin film cracking and delamination are organic packaging failure modes that result from the global thermal expansion mismatch between the package and silicon plus local thermal expansion mismatch among various silicon build up interconnect metal and passivation materials. The risk of these two failure modes is different between aluminum and copper silicon interconnects. Modeling and experimental data suggest the risk of silicon passivation film cracking and delamination is no longer a major reliability issue as it was in the aluminum interconnect technologies, due to the planar surface topography in copper damascene and the lower coefficient of thermal expansion.

Accelerated stress testing methodology to risk assess silicon-package thermomechanical failure modes resulting from moisture exposure under use condition

IC components are exposed to moisture and thermal cycles during chip-package-board assembly and in their end use conditions. Moisture exposure influences the mechanical integrity of silicon backend dielectrics, assembly/packaging materials and packages. Reliability performance under accelerated stresses that simulate use conditions are often a critical factor in choice of materials, processing options and design rules. A complete assessment of the cumulative environmental exposure from chip-package assembly, shipment/storage, board system assembly, through end-customer use is required to guarantee product performance and reliability. This paper will detail these end user environments and use failure mode/mechanism specific acceleration models to develop accurate accelerated life testing plans and requirements. These requirements will then be compared to JEDEC standards based requirements and a need for re-calibration of these standards to more appropriate temperatures and stress durations will be highlighted.

Predictive reliability modeling for flipchip interconnect bump extrusion

As next generation packages and package interconnects continue to extend the reliability performance envelope of current designs and materials it is necessary to predict the limitations of the current package and assembly process. The flip-chip, multi-layer Organic Land Grid Array (OLGA) package was developed for the current and future generations of microprocessors and chipsets to be used in applications ranging from servers, desktops and laptops to embedded applications. During normal processing voids in the epoxy underfill between the package and die occur as a result of moisture evaporation and underfill reaction byproducts during dispense and cure. During temperature cycling the lead-tin bump material is extruded into adjacent voids resulting in electrical shorts. As bump pitches are reduced, the risk of bump extrusion failures post temperature cycle increases. A predictive model to assess the potential reliability risk of bump extrusion over the component lifetime was needed prior to process qualification and pitch reduction. Analysis of the experimental data showed that the variables that modulate bump extrusion are void count, bump pitch, bump layout, underfill properties and temperature cycle condition. Using the failure rate and extrusion rate, an empirical reliability model was derived to predict bump extrusion failure rates based on the key variables. Intrinsic and empirical reliability modeling techniques documented in this manuscript can be used to assess the impact of bump pitch reduction, new process evaluations and manufacturing capability planning as related to flip-chip die-package bump extrusion.

The copy exactly! Evolution story: High reliability fungible output based solely upon matching

The Copy Exactly! methods have evolved throughout a twenty-five year journey from initial process tool configuration and bill of materials matching to include factory infrastructure, human factors, process controls, and process indicators matching. These methods have delivered high reliability across billions of microprocessors largely without dedicated reliability monitoring systems. How is this possible? CE! is an extensive system of matching that is integrated into the manufacturing network. Present day CE! 2.0, correlates development certification and process qualification data to high volume, online process control systems with inline quality and reliability monitoring. Online systems enable alternatives to traditional offline, ongoing reliability monitors which cannot detect problems close to the source nor time proximity with respect to occurrence of issues. We review these incorporations with a demonstration of results on Intels 14nm logic technology across four factories.

The state of Pb-free solder — A joint reliability overview

Over the past decade the electronics components industry successfully transitioned from the use of leaded solder to lead-free (Pb-free) solders in response to growing environmental health concerns related to heavy metals and other substances. Pbfree components in general are in compliance to meet the European restriction of hazardous substances (RoHS) directives. During the transition period to Pb-free surface mount, numerous issues were raised about the selected alloys, the board assembly process and reliability. Early Pb-free reliability concerns were due to incomplete analytical understanding of the Tin-Silver-Copper solder creep-fatigue behavior, difficulty in computing the magnitude of ball grid array (BGA) relative displacements or strains and lack of product field history. Since then the failure mechanisms were characterized and many models are in common use for reliability estimation and design. This manuscript revisits the initial concerns, reliability model use evolution and summarizes the current understanding that has resulted in a decade of reliable field operation for the Pb-free SAC solders selected.

Semi-empirical stress/energy-based acceleration of temperature cycling failure

Acceleration models used in microelectronic packaging are important for determining failure estimates during a products useful life. However, many of the models used in determining qualification requirements are based on empirically observed trends in historic fail modes and are parameterized based on extrinsic factors such as cycling temperature range. As new materials and packaging configurations lead to new failure modes, it is important that the acceleration is parameterized based on intrinsic factors such as stress, strain, and energy in order to accurately extrapolate end user failure rate estimates. This work proposes an acceleration model for thermomechanical cycling based on intrinsic accelerating factors.

Acceleration of chip - Package failures in temperature cycling

IC components experience temperature and power cycles during operation in their end use environments. They also experience cold temperature exposures during shipping. These temperature cycles influences the mechanical integrity of silicon backend dielectrics, assembly/packaging materials and packages. A complete assessment of the cumulative number of temperature cycles and temperature extremes from shipping/storage and through end-customer use is required to guarantee product performance and reliability. This paper will show data from accelerated temperature cycling on IC components and use these data to develop acceleration models for observed failure modes. These models will be used in conjunction with known use conditions to estimate lifetime requirements. These lifetime requirements will then be compared to JEDEC standards based requirements and a need for recalibration of these standards to more appropriate temperature cycle conditions and durations where will be highlighted. The influence of die package geometric factors on reliability performance will be shown. Some artifacts associated with stressing IC packages to extreme cold temperatures well outside of their intended use conditions will also be described.