J. Hicks

BTI reliability of 45 nm high-K + metal-gate process technology

In this paper, bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed. Transistors with an unoptimized HK film stack in the early development phase exhibited pre-existing traps and large amount of hysteresis that was consistent with literature. The optimized and final HK process demonstrated NMOS and PMOS BTI on HK+MG transistors that are better than that of SiON at matched E-fields and comparable at targeted 30% higher use fields. The final process also showed no hysteresis due to fast traps thereby allowing us to characterize its intrinsic degradation mechanism. On the optimized process, NMOS BTI is attributed primarily to electron trapping in the HK bulk and HK/SiON interfacial layer (IL) regions. PMOS BTI degradation, on the other hand, is mainly interface driven and is found to be very similar to that observed on conventional SiON transistors.

Microprocessor reliability performance as a function of die location for a 0.25 /spl mu/, five layer metal CMOS logic process

In this paper, we present the results of multiple correlations between reliability (infant mortality and other reliability metrics) and yield on a die level basis for an advanced microprocessor fabricated using a 0.25 /spl mu/m, five layer metal CMOS logic process. Traceability information was programmed into each unit; infant mortality of edge die verses center die, effects of unusual sort yield signatures on infant mortality, alternating row effects, and the sources of variability of burn-in failures were investigated. The model with reliability defect density proportional to yield defect density was found to be in excellent agreement with experimental data over a wide range of yield values. The x-y die position yield was found to be an excellent predictor of infant mortality. The variation in infant mortality from wafer to wafer was found to be twice the lot to lot variation, consistent with the large number of single wafer processing tools used on advanced fabrication processes. As the traceability information is part of the standard manufacturing flow, this analysis was performed using a very large 1 million unit sample size. Die near the edge of the wafer were found to have worse reliability than those near the center; certain die locations were particularly poor. Unusual yield signatures at wafer sort often showed the same map of failures in burn-in. The level of resolution possible from a die level analysis also allowed us to identify specific tools and interactions between tools in the fabrication process which were responsible for reliability failures.

Intrinsic transistor reliability improvements from 22nm tri-gate technology

This paper highlights the intrinsic reliability capabilities of Intels 22nm process technology, which introduced the tri-gate transistor architecture and features a 3rd generation high-κ/metal-gate process. Results are detailed from all traditional transistor reliability mechanisms, including BTI, TDDB, SILC, and HCI. In addition, characteristics unique to this transistor architecture and process technology are described.

Frequency and recovery effects in high-κ BTI degradation

Net end-of-life aging prediction under realistic use conditions is the key objective for any product aging model. In this paper, a net degradation model is introduced and effects such as recovery, subsequent degradation, frequency, duty cycle, and recovery bias are evaluated. The high-κ recovery behavior observed is consistent with SiO2 gate stacks, which allows the use of SiO2 models to predict recovery in both NMOS and PMOS high-κ transistors.

Self-heat reliability considerations on Intel's 22nm Tri-Gate technology

This paper describes various measurements on self-heat performed on Intels 22nm process technology, and outlines its reliability implications. Comparisons to thermal modeling results and analytical data show excellent matching.

Bias temperature instability variation on SiON/Poly, HK/MG and trigate architectures

A summary of NBTI variation is reported on large data-sets across five generations of Intel technologies (90 nm to 22 nm) and a comparison of statistical frameworks is utilized to show the universality of variation metrics across generations. Large volumes of data and modeling are emphasized as critical to enable accurate simulations of NBTI in extreme tails.

Soft Error Rate Improvements in 14-nm Technology Featuring Second-Generation 3D Tri-Gate Transistors

We report on radiation-induced soft error rate (SER) improvements in the 14-nm second generation high- k + metal gate bulk tri-gate technology. Upset rates of memory cells, sequential elements, and combinational logic were investigated for terrestrial radiation environments, including thermal and high-energy neutrons, high-energy protons, and alpha-particles. SER improvements up to ~ 23× with respect to devices manufactured in a 32-nm planar technology are observed. The improvements are particularly pronounced in logic devices, where aggressive fin depopulation combined with scaling of relevant fin parameters results in a ~ 8× reduction of upset rates relative to the first-generation tri-gate technology.

Dielectric breakdown in a 45 nm high-k/metal gate process technology

In this paper, we present extensive breakdown results on our 45nm HK+MG technology. Polarity dependent breakdown and SILC degradation mechanisms have been identified and are attributed gate and substrate injection effects. Processing conditions were optimized to achieve comparable TDDB lifetimes on HK+MG structures at 30% higher E-fields than SiON with a reduction in SILC growth. Extensive long-term stress data collection results and a change in voltage acceleration are reported.

Characterization of SILC and its end-of-life reliability assessment on 45NM high-K and metal-gate technology

Stress Induced Leakage Current (SILC) has been observed on non-optimized high-K (HK) and metal-gate (MG) transistors. Large NMOS PBTI degradation and correlation to SILC increase on such gate stack is a result of large trap generations in the bulk-HK. This poses a long term reliability concern on product standby power and can limit the operating voltage if not suppressed. On an optimized HK+MG process, we demonstrate that SILC has been suppressed. The transistor level SILC data, model and Product burn-in stress data support this. With optimized process, SILC has no impact on products made of 45nm HK+MG transistors.

Transistor reliability variation correlation to threshold voltage

MOSFET reliability data are often represented as a function of gate overdrive (VG-VT) with the implicit assumption that overdrive is the appropriate normalizing parameter. While this can be true for some specific sources of variation, reliability does not necessarily track gate overdrive. This paper explores systematic and random sources of variation in TDDB, BTI, and hot carrier degradation data in Intels tri-gate technologies. We find that random variation captured within a baseline of reliability data does not, in general, trend with overdrive. However, some sources of systematic variation are correlated or, interestingly, anti-correlated with overdrive.