Sudarshan Rangaraj

Accelerated stress testing methodology to risk assess silicon-package thermomechanical failure modes resulting from moisture exposure under use condition

IC components are exposed to moisture and thermal cycles during chip-package-board assembly and in their end use conditions. Moisture exposure influences the mechanical integrity of silicon backend dielectrics, assembly/packaging materials and packages. Reliability performance under accelerated stresses that simulate use conditions are often a critical factor in choice of materials, processing options and design rules. A complete assessment of the cumulative environmental exposure from chip-package assembly, shipment/storage, board system assembly, through end-customer use is required to guarantee product performance and reliability. This paper will detail these end user environments and use failure mode/mechanism specific acceleration models to develop accurate accelerated life testing plans and requirements. These requirements will then be compared to JEDEC standards based requirements and a need for re-calibration of these standards to more appropriate temperatures and stress durations will be highlighted.

Rapid die heating for low-stress die attach

During traditional isothermal die attach assembly, significant thermomechanical stress develops in the solder joints between the die and board. The coefficient of thermal expansion (CTE) of the silicon die and the woven composite circuit board materials are widely different. Under isothermal die attach, there is, hence, a mismatch between the thermal expansion displacements of the die and substrate, thereby leading to stress in the solder joints and die interconnect layers. One avenue to alleviate these stresses is to use alternate die attach processes that rely on localized heating of the die and solder joints so as to minimize the thermal expansion displacement mismatch. Die attach stress can be reduced significantly through rapid die heating (RDH), which results in the die being hotter than the board at the solder solidification point. Analytical modeling shows that RDH can reduce residual stress by up to 80% compared to traditional, isothermal die attach processing. Limited experimental results demonstrate 40% stress reduction to date. This paper will detail these results and physical analysis of the resulting solder joints.

Mechanical Design and Analysis of Land Grid Array (LGA) Sockets

Sockets offer a cost effective and high-volume manufacturing friendly interface between CPU packages and motherboards. Land-grid-array (LGA) technology offers avenues to enhance the electrical performance of sockets over its predecessors e.g. pin grid array (PGA) technology. The present paper will describe various technical challenges encountered in the design of Intel’s LGA sockets. The recently launched LGA775 socket will be used as a case study. Methods adopted to overcome these design challenges and successfully implement LGA sockets will be discussed. Design features like direct socket loading (DSL), various issues related to the design of socket housings, LGA contact design optimization and socket reliability enhancement under stresses such as thermal cycling, mechanical shock, vibration and bake will be discussed. DSL is an integrated mechanism that enables application of a compressive mechanical load between the LGA contact pins on the socket and the package LGA pads, so that their interfaces achieve and maintain electrical continuity through the socket design life. Similarly, optimizing the design of the socket contacts significantly impacts the stressing, reliability of the second level interconnect (SLI) ball grid array (BGA) that connects the LGA775 to the motherboard. The successful implementation of these designs is achieved through a combination of geometric tolerance stack analysis, numerical modeling studies, detailed experiments, reliability testing and correlation between these. The details of the same are be discussed in this article.Copyright

Pressure-Compensated Chip Attach: A Low-Stress Silicon Bump Reflow Process

Assembly of silicon onto FR4-based organic substrates using flip-chip process continues to pose substantial thermomechanical challenges largely due to the disparate coefficients of thermal expansion (CTEs) of silicon and substrate. In flip-chip packaging, this CTE mismatch causes mechanical stresses in the chip-to-substrate interconnection bumps and the mechanically fragile interlayer dielectric (ILD) within the chip, leading to fracture and delamination. A novel process called pressure-compensated chip attach (PCCA) is presented, where the silicon chip is attached to the substrate by reflowing the solder bumps while maintaining the chip and substrate in a controlled hydrostatic pressure environment. Experiments show that the new PCCA process reduced the silicon test-chip warpage by 40% and eliminated ILD cracking.

Acceleration of chip - Package failures in temperature cycling

IC components experience temperature and power cycles during operation in their end use environments. They also experience cold temperature exposures during shipping. These temperature cycles influences the mechanical integrity of silicon backend dielectrics, assembly/packaging materials and packages. A complete assessment of the cumulative number of temperature cycles and temperature extremes from shipping/storage and through end-customer use is required to guarantee product performance and reliability. This paper will show data from accelerated temperature cycling on IC components and use these data to develop acceleration models for observed failure modes. These models will be used in conjunction with known use conditions to estimate lifetime requirements. These lifetime requirements will then be compared to JEDEC standards based requirements and a need for recalibration of these standards to more appropriate temperature cycle conditions and durations where will be highlighted. The influence of die package geometric factors on reliability performance will be shown. Some artifacts associated with stressing IC packages to extreme cold temperatures well outside of their intended use conditions will also be described.

Low-k ILD reliability through chip-package assembly: Engineering appropriate stress tests and process certification criteria

Inter-layer dielectric (ILD) materials used in silicon chip backend layers tend to be mechanically fragile, and the industry trend is towards ILD materials with even lower dielectric constants and fracture toughness. Flip-chip packaging with lead-free solder materials imposes significant thermo-mechanical stresses on these fragile ILD films due to the thermal expansion miss-match between the silicon chip and organic package. To guarantee low-K ILD integrity through chip-package assembly and reliability in use with adequate margin it is crucial to understand and quantify the sources of stress, their variability and use this information to define the right stress tests and success criterion. This paper will present a systematic study of the modulators of low-K ILD stress using empirical data from 45, 32 and 22nm Intel processes as well as finite element modeling. Key sources of variation in the silicon chip process as well as the chip-package assembly process will be examined and their effects on ILD stress will be quantified. This information will be used to assess the amount of over-stress needed to account for worst case manufacturing variation in silicon chip and chip - package assembly processes. Two approaches to characterization tests that provide the required over-stress will be discussed. The first approach is based on chip processing and package design skews to increase the ILD stress while the second approach relies on cooling the chip-package to below room temperature post-assembly in order to exaggerate the thermal expansion miss-match and over-stress the ILD layers. Process certification criteria to guarantee ILD reliability will be presented and optimized sampling plans to demonstrate that these goals are met will also be discussed.