Albert Fazakas

Adaptive Microarray Image Acquisition System and Microarray Image Processing Using FPGA Technology

The present paper proposes an adaptive hardware implementation for a microarray image acquisition system, which is mandatory for implementing hardware algorithms for processing microarray images. Processing techniques for microarray image are also described, together with a hardware implementation of a spot border detection algorithm. The hardware implementation takes advantage of parallel computation capabilities offered by FPGA technology. Results which prove time and cost efficiency are presented for both hardware implementations.

Hardware implementation of microarray image segmentation

The present paper proposes an acquisition system for microarray image on an FPGA based platform, together with a hardware implementation of image segmentation for cDNA micro-array images. The hardware implementation takes advantage of parallel computation capabilities offered by FPGA technology.

Novel Image Rejection Filter Based on Neural Networks

In this paper a novel image rejection algorithm based on neural networks is proposed. The low-IF receiver architecture and the phenomena of I/Q imbalance (also referred as image interference) are described. The proposed filter is an enhancement of a complex LMS adaptive filter, which separates the desired and image signals, but the recovered signal still suffers from the effects of imbalance parameters. This is corrected by the proposed filter. Simulink simulations were performed in order to prove the functionality of the novel filter. The simulations prove the convergence and stability of the filter. The necessary sample number is given to achieve -60 dB image rejection.

Novel FIR implementation for acoustic signal processing

This paper proposes a novel FIR filter hardware implementation. In applications where acoustic signals are processed (acoustic echo cancellation, reverberation, digital audio effects) the required orders of the filters might be too high to fit into hardware platforms for real-time processing The number of delay elements required by traditional FIR implementations equals to the filter order. Our proposal explores the capability to process acoustic signals at much higher frequencies than the sampling rate. The resulting hardware requires two memories, one used to store the signal samples and the other one for the filter coefficients. The hardware also requires one multiplier and an accumulator. The feasibility of the proposed system is proven by the implementation of a digital reverberator on an FPGA platform.

An Analog Circuit for Computing Radial Basis Kernels

We present in this paper an analog CMOS current-mode circuit for calculating radial basis kernels. It represents the main component of some analog or mixed-signals support vector machine (SVM) classifiers. This circuit will be used in a PSpice simulation environment for VLSI circuits including SVMs for image detection, implemented in hardware, a useful tool not only in our multidisciplinary research but also in education. Simulations have been performed proving the validity of design and circuit functionality

A MONOCIP integrated BT implementation of a current feedback Op Amp

This paper presents our first attempts to implement a current-feedback Op Amp. We considered the possibility of using the ICCE full custom technology MONOCIP. We presents also the performances of this new circuit, comparatively with other existing CFB-OA (OPA 603).