Lelia Festila

A Reconfigurable and Programmable Filter for Software Defined Radio Based on a Transconductor-Capacitor Analog Array

This paper presents a reconfigurable and programmable analog array intended to support the implementation of the filter stage in a software defined radio (SDR) wireless transceiver. The analog array is designed using the transconductor-capacitor (Gm-C) technique and may implement a wide variety of analog filters of programmable order and transfer function. The filtering stage implemented by the analog array is envisioned as part of a combined low-IF/zero-IF receiver architecture for an SDR transceiver. A modular method of synthesizing various order state-variable filters is used as tool for demonstrating the capabilities of the analog array. Different filters have been modeled, in both the complex and real domains, to demonstrate the capability of the analog array.

A double-layer genetic algorithm for Gm-C filter design

Although analog circuits play an important role in Systemson-a-chip, their design is effort and time consuming. Automated design methodologies are elaborated to overcome drawbacks resulting from human design. This paper proposes a double-layer on-line genetic algorithm-based optimization method for use in the automated design of Gm-C filters. To accomplish on-line circuit evolution, a Matlab-Eldo interface is proposed for communication of the GA with the circuit simulation environment. After a presentation of the Gm-C filter with an analysis of filter tunability, the two layers of the evolution are presented: raw filter design and fine-tuning of the filter characteristic. Simulation of the evolutionary algorithm proves the efficiency of the double-layer approach in reducing design time for a GA-only optimization technique.

Analog Multiplying/Weighting VLSI Cells for SVM Classifiers

VLSI support vector machine classifiers require a large amount of calculations, therefore their implementation needs high density, high speed and low power circuits. In a SVM architecture based on a multiplying law the main building blocks are multipliers. We propose in this paper multiplying and weighting cells, developed by using a model consisting of a compound of two inverse non-linear functions. This procedure is suitable for VLSI implementation because it permits the use of simple nonlinearized standard DA cells that compensate each other nonlinearities to obtain an extended domain of operation. The resulted weighting/multiplying cells were analyzed and tested by simulations.

Modular Log-domain Multipliers for SVM Classifiers

We propose modular log-domain structures for implementing analog multipliers intended to be used in SVM (support vector machines) classifiers and neural network structures

Hybrid device interoperability in intelligent building systems

Intelligent Building Management Systems (BMSs) are more widely used in various buildings that are extending beyond usual networks, including any imaginable electronic device. There are many BMSs, each one having their own architecture using different protocols, standards and working on various communication interfaces like cable, power line or radio frequency. There are many devices that are communication enabled but due to lack of a unifying standard interoperability between devices is impossible. Founded by this observation the basic idea of this paper is to propose a solution for this problem by using Software Defined Radio (SDR) technology to design a hybrid (wired/wireless) gateway platform. A test system had been developed to test gateway communication with some wireless sensors. This solution could bring a higher level of flexibility to BMSs and therefore, various devices working on future standards and protocols would be easily integrated into current BMSs without major modifications.

Towards Reconfigurable Circuits Based on Ternary Controlled Analog Multiplexers/Demultiplexers

The multiplexers are used in a wide range of applications. At present, they are controlled by binary signals. To reduce the number of interconnections, ternary signals are proposed to be used to control analog multiplexers/demulti-plexers. The analog multiplexers/demultiplexers are realized with CMOS transmission gates, their control circuits being designed using CMOS ternary inverters. The technology used to design ternary inverters is SUS-LOC. A 3-to-1 analog multiplexer is proposed in the design of a reconfigurable ternary inverter.

A New CCII-Based Universal Biquad

This paper proposes a CCII-based structure from which one can derive, with minimum of adjustments, a series of biquads, able to realize not only the most usual second-order transfer functions - low-pass, band-pass, all-pass - but also transfer functions with imaginary and complex zeroes. Other interesting features of this universal biquad are its cascadability and the fact that it provides the orthogonal tuning of its transfer function coefficients. A design example illustrates the wide range of sizing and tuning options available

Log-Domain Binary SVM Image Classifier

We propose in this paper a binary log-domain Support Vector Machine classifier based on a polynomial decision function. To implement such a classifier log-domain multipliers proposed by the authors are used. For the parallel-serial implementation a log-domain summing amplifier and a current mode comparator are also needed. Current mode log-domain design is used for its low voltage, low power and high frequency characteristics. The resulted classifier is simulated taking into account real parameters of transistors in BiCMOS technology.

Four quadrant log-domain analog current multiplier

In this paper we propose a log-domain four quadrant current multiplier. This circuit can be used in modular log- domain VLSI architectures. The simplicity, low power consumption and high frequency operation recommend it for real time applications.

Improving Measuring Procedures in DC-DC Converters

The PSpice functions used for measuring the power, average and root mean square are not accurate enough because of using specific techniques like products or filters. We created fast and precise specialised behavioural blocks that obtain the power, average and root mean square values of the signals by applying an integral relation. The computation is done after the transitory regime is finished and so the values are constant and easy to be read. The method was used for measurements in DC-DC converters, where the switching period is very small (10-20 museconds).