Robert Groza

Analog Multiplying/Weighting VLSI Cells for SVM Classifiers

VLSI support vector machine classifiers require a large amount of calculations, therefore their implementation needs high density, high speed and low power circuits. In a SVM architecture based on a multiplying law the main building blocks are multipliers. We propose in this paper multiplying and weighting cells, developed by using a model consisting of a compound of two inverse non-linear functions. This procedure is suitable for VLSI implementation because it permits the use of simple nonlinearized standard DA cells that compensate each other nonlinearities to obtain an extended domain of operation. The resulted weighting/multiplying cells were analyzed and tested by simulations.

Modular Log-domain Multipliers for SVM Classifiers

We propose modular log-domain structures for implementing analog multipliers intended to be used in SVM (support vector machines) classifiers and neural network structures

An all-digital frequency locked loop and its linearized S-domain model

The proposed all-digital frequency locked loop features a digitally controlled oscillator, a counter & latch as a frequency sensor and an accumulator in the control loop. The number of oscillation cycles are counted during a logic high of the reference signal and it is subtracted from a desired value set by the user, thus an error signal is obtained. The error is accumulated, and a digital control word is formed for the digitally controlled oscillator. Discrete time domain equations are devised for the proposed ADFLL, and the convergence to the desired frequency is proven. Moreover, the analysis is completed with the s-domain linearized model of the system. Numerical results comprise simulations carried out in (i) a logic simulator for the Verilog behavioral description of the ADFLL and (ii) a PSPICE simulation for the s-domain model.

Log-domain low-pass biquads with independent and continuous tuning of main parameters

This paper presents two new Externally Linear Internally Nonlinear (ELIN) low-pass second order filters. The first topology was derived from a standard state-variable biquad by using a LIN-ELIN transformation. The resulting structure was improved in order to simplify its implementation. Both biquads allow for orthogonal tuning of their Ho, ω0 and Q. They can be tuned continuously by varying only DC bias currents. Simulation results demonstrate the analytical analysis.

Programmable log-domain low pass filter

This paper presents a programmable low-pass filter implemented with log-domain building blocks; the blocks have Externally Linear Internally Nonlinear (ELIN) structures derived using LIN-ELIN transformations. The order of the proposed filter transfer function can be set to 3rd, 4th or 5th by a digital control word; the main filter parameters can be tuned/adjusted by using the bias currents of the building blocks.

Log-Domain Binary SVM Image Classifier

We propose in this paper a binary log-domain Support Vector Machine classifier based on a polynomial decision function. To implement such a classifier log-domain multipliers proposed by the authors are used. For the parallel-serial implementation a log-domain summing amplifier and a current mode comparator are also needed. Current mode log-domain design is used for its low voltage, low power and high frequency characteristics. The resulted classifier is simulated taking into account real parameters of transistors in BiCMOS technology.

Four quadrant log-domain analog current multiplier

In this paper we propose a log-domain four quadrant current multiplier. This circuit can be used in modular log- domain VLSI architectures. The simplicity, low power consumption and high frequency operation recommend it for real time applications.

Improving Measuring Procedures in DC-DC Converters

The PSpice functions used for measuring the power, average and root mean square are not accurate enough because of using specific techniques like products or filters. We created fast and precise specialised behavioural blocks that obtain the power, average and root mean square values of the signals by applying an integral relation. The computation is done after the transitory regime is finished and so the values are constant and easy to be read. The method was used for measurements in DC-DC converters, where the switching period is very small (10-20 museconds).

Digitally controlled current-mode quadrature oscillator

A digitally controlled current-mode quadrature oscillator (DCC-MQO) is proposed. The circuit consist of four cascaded log-domain first order low-pass filter and a digitally programmable current division network. The lossy log-domain integrator gain and time constant can be adjusted using the bias currents of the logarithmic and exponential building blocks. The programmable current division network provides the bias currents for the log-domain cells which can be adjusted using a digital control word. The building blocks were implemented in a generic 180nm BiCMOS process and Spice simulation were performed to demonstrate de viability of the design.

Current-mode Configurable Analog Block

The paper presents a novel ELIN analog configurable block (CAB). Using this CAB one can implement first and second order transfer functions such as lossy and lossless integrator, low-pass, high-pass, band-pass and band-stop biquads. For implementing the building blocks, we used log-domain cells. Due to their simple structures and current-mode operation this circuits are suitable for low-voltage, low-power applications such as field programmable analog arrays. The circuits were implemented using a generic 180 nm BiCMOS process. SPICE analyses were performed to validate the design.