Alberto O. Adan

Analytical threshold voltage model for ultrathin SOI MOSFETs including short-channel and floating-body effects

Short-channel effects (SCE) in ultrathin silicon-on-insulator (SOI) fully depleted (FD) MOSFETs are analyzed and an analytical model for threshold voltage, including the kink effect, is presented. The proposed model accounts for (1) a general nonuniform channel doping profile, (2) the drain-induced V/sub th/- lowering enhancement resulting from the interaction of (a) impact ionization, (b) floating-body, and (c) parasitic-bipolar effects. Good agreement between the proposed model and experimental data is demonstrated. Impact ionization and floating-body effects dominate V/sub th/ lowering for drain voltages larger than V/sub dk//spl sime/B/sub i/./spl lambda//sub i//3, where B/sub i/ is the impact ionization coefficient, and /spl lambda//sub i/ is the impact ionization length, a structural parameter which, for a single-drain SOI MOSFET, coincides with the SCE characteristic length /spl lambda/.

SOI as a mainstream IC technology

Silicon on insulator (SOI) based devices have been a research theme for about two decades. The advantages over bulk Si are clear and SOI substrates have been expected to break into the mainstream CMOS IC industry. Until now, these expectations have not been realized. The reasons behind this include: (i) SOI wafer availability, quality and cost; (ii) SOI MOSFET floating body effects and lower breakdown voltage; and (iii) economic reasons that propel bulk CMOS advances in circuit techniques and process technology. This situation is now changing. Battery operated portable devices are called to perform advanced functions that include communication in the RF spectrum at frequencies in the 400 MHz to 2.5 GHz range, as well as complex signal and graphic processing. The low voltage, low power and high performance requirements are showing the limitations of bulk CMOS and are opening a new opportunity for SOI. In this paper, the status of SOI device applications and manufacturing considerations are reviewed.

Physical Model of Noise Mechanisms in SOI and Bulk-Silicon MOSFETs for RF Applications

The noise mechanisms at high frequencies in MOSFETs are analyzed and an analytical model is presented for devices operating at gigahertz frequencies. The proposed model is applied to floating body silicon-on-insulator (SOI) as well as bulk-silicon MOS transistors and experimentally verified. The model accounts for the mechanisms of 1) channel thermal noise; 2) shot-noise due to impact ionization; and 3) substrate back-gate-coupled thermal noise. Compact, closed-form analytical expressions of the noise power spectral density and the minimum noise figure (NF) are presented. At the same technology level, the experimental data and the model show that SOI MOSFETs are able to attain lower NF than bulk-silicon devices by reduction of the back-gate transconductance. However, the higher drain electric field in the SOI, and the parasitic bipolar action and floating body enhance impact-ionization-associated shot-noise, which becomes the limiting noise mechanism at drain voltages higher than the drain onset voltage of ldquokinkrdquo effect. A correlation between the onset voltage and the DC electrical characteristics is shown.

Robust 600 V GaN high electron mobility transistor technology on GaN-on-Si with 400 V, 5 µs load-short-circuit withstand capability

A 600 V normally-ON GaN high-electron mobility transistor (HEMT) technology with an intrinsic specific ON resistance R on A = 500 mΩmm2 and a breakdown voltage of BV dss ~ 1100 V is described. A novel high-power 30-A-class GaN-Si MOSFET cascode device with a back-side source Si laterally diffused MOSFET (LDMOSFET) and an embedded clamp diode are employed to enable the GaN HEMT to withstand 400 V and a more than 5 µs load short circuit condition, as required in switching inverter applications. Considerations for improvement of the GaN lateral HEMT short-circuit withstand capability are addressed.

Analytical short-channel effect model for ultra-thin SOI MOSFETs including floating body effects

Summary form only given. SOI MOSFETs implemented on ultra-thin superficial Si film are regarded as promising candidates for the deep-half micron CMOS generation due to their excellent characteristics. To assess the transistor and technology design, however, a compact analytical model that includes the important floating body effects is needed. In this work, a physics-based analytical model for the threshold voltage Vth, that considers (i) a more general non-uniform channel profile and (ii) also the floating body effects, and parasitic bipolar action, that greatly degrade DIBL, is presented. Threshold lowering in the saturation regime is important since it determines Ioff leakage and standby current. These effects have not been included in previous models, and therefore are limited in their predictions.

The off leakage in SOI-MOS transistors and the impact on the standby current of ULSI's

Summary form only given. The application of SOI-CMOS to low-voltage, battery-powered devices is facing the practical trade-off between low threshold voltage and off-state leakage current. For typical portable electronic equipment, the specification for standby power dissipation restricts the MOSFET off-current to I/sub doff/<10 pA//spl mu/m, which should be compared with I/sub doff//spl sim/1 nA//spl mu/m in high-speed microprocessors (Leonbandung et al., 1998). In this paper, we investigate the off-current mechanism in SOI MOSFETs and its relationship with the ICs standby current for quantitative modeling. The model parameter extraction techniques are also described.

A Robust 600V GaN HEMT Technology on GaN-on-Si with 400V, 5μsec Load-Short-Circuit Withstand Capability

A 600V normally-ON GaN HEMT technology, featuring an intrinsic RonxA=500mΩ.mm2 at BVdss~1100V, is described. A novel high-power 30A GaN-Si MOSFET Cascode, with Si-LDMOS back-side source and embedded clamp diode is implemented. For the first time, a 30A-class GaN Cascode is able to withstand 400V, >5μsec load-short circuit condition, as required in switching inverter applications.