Alberto Scandurra

Skew Insensitive Physical Links for Network on Chip

The increasing complexity, in terms of both physical dimension and performance demand of current systems on chip (SoCs) led to the development of new suitable interconnect architecture, leveraging on computer network technology, called network on chip (NoC). This paper describes two architectures of advanced physical link for NoC, the former based on mesochronous technology, the latter based on asynchronous

Optical Interconnects for Network on Chip

This paper resumes some state-of-the-art results of research in view of the realization of optical interconnects as physical link for network on chip (NoC). Emphasis is given in particular to amorphous silicon technology for its actual technological compatibility with CMOS microchips

Wavelength division multiplexed photonic layer on CMOS

Optical network on chip (ONoC) architectures are emerging as potential contenders to solve congestion and latency issues in future computing architectures. This paper describes WADIMOS, an EU funded research project aiming to demonstrate a complex photonic interconnect layer on CMOS. This incorporated multichannel microsources, microdetectors and various advanced wavelength routing functions directly integrated with electronic driver circuits. Design methods and system-level models compatible with an industrial NoC exploration environment were developed to enable exploration of application scenarios for such electro-photonic ICs, in an on-chip optical network context.

Optical network-on-chip reconfigurable model for multi-level analysis

Optical network-on-chip (ONoC) is a well accepted emerging technology for use as a communication platform for systems-on-chip (SoC). Its heterogeneous nature dictates developing a hierarchical model and tools for its design and analysis. This paper presents a reconfigurable ONoC model that can be used for analyzing the network at three hierarchical levels: system level, behavioral level, and physical level. At system level, the proposed ONoC model can be used to evaluate the network performance metrics (e.g. latency and throughput). At behavioral level, the model can be used to analyze the functionality of the whole ONoC from the interaction and the integration of its constituent building blocks. At the physical level, the model can be used to analyze the effect and verify the joint feasibility of optoelectronic and photonic devices specifications for reliable data communication and can further be used as a reference golden model during the design phase of the physical devices. The proposed model has been integrated successfully inside an industrial simulation environment (ST GenKit) using an industrial standard (VSTNoC) protocol.

Effective full-duplex Mesochronous Link Architecture for Network-on-Chip Data-Link layer

The increasing complexity of system on chip (SoC) architectures and the physical issues due to the CMOS technology scaling, led to explore new solutions to build effective on-chip interconnection and communication infrastructures. Network on chip (NoC) paradigm has been proposed as architectural solution mainly for overcoming scalability and flexibility limitations. However, advanced techniques to mitigate wire-delay effects have to be employed to reduce the impact of physical issues. Globally asynchronous locally synchronous (GALS) paradigm has been selected to this purpose as solution to implement the NoC physical layer, and many different approaches to design GALS-based NoC can be used. In this paper a full-duplex mesochronous link architecture, for which a patent has been submitted, is proposed to effectively implement the GALS paradigm in the STNoCtrade system. Such a link, exploiting the service provided by the newest mesochronous physical layer known as SKIL, effectively implements the mesochronous communication at data-link layer and enables to overcome some important issues of the previous mesochronous solutions.

Silicon Photonics: The System on Chip Perspective

This chapter describes possible applications of silicon photonics to the System on Chip (SoC) domain. Systems on Chip (SoCs) are complex systems containing billions of transistors integrated in a unique silicon-chip, implementing even complex functionalities by means of a variety of modules communicating with the system memories and/or between them through a proper communication system. The higher and higher integration density is becoming such that many issues arise when a SoC has to be integrated, and electrical limits of interconnect wires are a limiting factor for performance. According to this scenario, a new technology is required for the on-chip interconnect, in order to overcome current physical and performance issues; one possible solution is the optical interconnect, exploiting the many benefits of light to transport information across the chip. From an industrial point of view it is fundamental that such a new technology be fully CMOS compatible, in order to be able to continue to use current SoC design methodologies as well as present manufacturing equipment for the whole electronic part of the chip. Many semiconductor industries are today investigating such a novel field and a number of projects are currently running in order to demonstrate the feasibility of such a revolutionary on-chip communication system relying on both CMOS technology and photonics.

Optical NoC design-parameters exploration and analysis

Optical network-on-chip (ONoC) is a well accepted emerging technology for use as a communication platform for system-on-chip (SoC). Due to its heterogeneous nature, tools for its design and analysis have become a necessity. In this paper, we present a tool for the exploration and validation of ONoC building block design parameters. The proposed methodology explores and verifies the joint feasibility of optoelectronic and photonic devices specifications for successful and reliable data communication. This is achieved through building a library of matching and chainable sets of optoelectronic and photonic devices. This library can be used for ONoC system-level design and analysis as well as during the design phase of these devices.

Relieving physical issues in new NoC-based SoCs

Many research activities in the area of Network on Chip (NoC) architectures have been performed. The results achieved up to now are quite attractive but often are not directly applicable because of technological reasons or implementation difficulty. In this paper an industrial experience is presented by introducing the approach followed to support the transition from the traditional interconnects to the NoC architectures. The paper mainly focuses on the strategy used to overcome physical issues and particularly the difficulty to perform system synchronization.

A new low-power N fold flip-flop with output enable

Flip-flops with output enable are crucial elements for the design of digital systems. With the aggressive scaling in feature sizes, they start to pose some challenging problems for designers. This is due to their synchronous nature that represents the main cause of both the high digital noise that they generate and the significant fraction of power that they consume essentially dynamically. In this paper we delve into the design of n-fold flip-flops with output enable. A new n-fold flip-flop exploiting the clock gating technique for both outputs enabling and power saving is presented. To evaluate its performance, an octal flip-flop was built according to the new proposed structure and compared to the main octal flip-flops used today. The different flip-flops were implemented in STMicroelectronics 65 nm process technology and simulated for the worst case condition where the switching activity is maximal. Post layout simulation showed that the new circuit provides the same functional performances as conventional solutions with significantly less power consumption, area and digital noise.

Interconnect Issues in High-Performance Computing Architectures

Systems on chip (SoCs) are complex systems containing billions of transistors integrated in a unique silicon chip, implementing highly complex functionalities by means of a variety of modules communicating with the system memories and/or between them through a proper communication system. Integration density is now so high that many issues arise when a SoC has to be implemented, and the electrical limits of interconnect wires are a limiting factor for performance. The main SoC building-block to be affected by these problems is the on-chip communication system (or on-chip interconnect), whose task is to ensure effective and reliable communication between all the functional blocks of the SoC. A novel methodology aiming at solving the problems mentioned above consists of splitting a complex system over more dice, exploiting the so-called system in package (SiP) approach and opening the way to dedicated high-performance communication layers such as optical interconnect. This chapter deals with the SoC technology, describes current solutions for on-chip interconnect, illustrates the issues faced during the SoC design and integration phases and introduces the SiP concept and its benefits.