Daniele Mangano

Skew Insensitive Physical Links for Network on Chip

The increasing complexity, in terms of both physical dimension and performance demand of current systems on chip (SoCs) led to the development of new suitable interconnect architecture, leveraging on computer network technology, called network on chip (NoC). This paper describes two architectures of advanced physical link for NoC, the former based on mesochronous technology, the latter based on asynchronous

Effective full-duplex Mesochronous Link Architecture for Network-on-Chip Data-Link layer

The increasing complexity of system on chip (SoC) architectures and the physical issues due to the CMOS technology scaling, led to explore new solutions to build effective on-chip interconnection and communication infrastructures. Network on chip (NoC) paradigm has been proposed as architectural solution mainly for overcoming scalability and flexibility limitations. However, advanced techniques to mitigate wire-delay effects have to be employed to reduce the impact of physical issues. Globally asynchronous locally synchronous (GALS) paradigm has been selected to this purpose as solution to implement the NoC physical layer, and many different approaches to design GALS-based NoC can be used. In this paper a full-duplex mesochronous link architecture, for which a patent has been submitted, is proposed to effectively implement the GALS paradigm in the STNoCtrade system. Such a link, exploiting the service provided by the newest mesochronous physical layer known as SKIL, effectively implements the mesochronous communication at data-link layer and enables to overcome some important issues of the previous mesochronous solutions.

Relieving physical issues in new NoC-based SoCs

Many research activities in the area of Network on Chip (NoC) architectures have been performed. The results achieved up to now are quite attractive but often are not directly applicable because of technological reasons or implementation difficulty. In this paper an industrial experience is presented by introducing the approach followed to support the transition from the traditional interconnects to the NoC architectures. The paper mainly focuses on the strategy used to overcome physical issues and particularly the difficulty to perform system synchronization.