Giuseppe Falconeri

Effective full-duplex Mesochronous Link Architecture for Network-on-Chip Data-Link layer

The increasing complexity of system on chip (SoC) architectures and the physical issues due to the CMOS technology scaling, led to explore new solutions to build effective on-chip interconnection and communication infrastructures. Network on chip (NoC) paradigm has been proposed as architectural solution mainly for overcoming scalability and flexibility limitations. However, advanced techniques to mitigate wire-delay effects have to be employed to reduce the impact of physical issues. Globally asynchronous locally synchronous (GALS) paradigm has been selected to this purpose as solution to implement the NoC physical layer, and many different approaches to design GALS-based NoC can be used. In this paper a full-duplex mesochronous link architecture, for which a patent has been submitted, is proposed to effectively implement the GALS paradigm in the STNoCtrade system. Such a link, exploiting the service provided by the newest mesochronous physical layer known as SKIL, effectively implements the mesochronous communication at data-link layer and enables to overcome some important issues of the previous mesochronous solutions.

Common Reusable Verification Environment for BCA and RTL Models

This paper deals with a common verification methodology and environment for SystemC BCA and RTL models. The aim is to save effort by avoiding the same work done twice by different people and to reuse the same environment for the two design views. Applying this methodology the verification task starts as soon as the functional specification is signed off and it runs in parallel to the models and design development. The verification environment is modeled with the aid of dedicated verification languages and it is applied to both the models. The test suite is exactly the same and thus it is possible to verify the alignment between the two models. In fact the final step is to check the cycle-by-cycle match of the interface behavior. A regression tool and a bus analyzer have been developed to help the verification and the alignment process. The former is used to automate the testbench generation and to run the two test suites. The latter is used to verify the alignment between the two models comparing the waveforms obtained in each run. The quality metrics used to validate the flow are full functional coverage and full alignment at each IP port.