Ale Imran

Asterisk Voice Exchange: An Alternative to Conventional EPBX

This paper highlights the design and implementation aspects of a VoIP based asterisk voice exchange, developing a fully functional voice exchange requires to set up a server based on Asterisk, connecting clients to that server with the help of soft phones and then configuring the soft phones with the server. Here in our implementation we have connected the clients to the server with the help of IAX protocols. The first part of the paper contains some introductory concepts about VoIP, followed by asterisks internal architecture. In the third part of the paper we discuss about the codecs and protocols used by the packet switching based PBX networks and finally we brush up about the design and implementation aspects.

Optimized Design of a 32-nm CNFET-Based Low-Power Ultrawideband CCII

CMOS technology faces significant challenges like tunneling effect, random dopant fluctuation, and line edge roughness at channel lengths below 45 nm. Carbon nanotube-based electronics seems to be a better prospect for extending the saturating Moores law because of its higher mobility, scalability, and better channel electrostatics. This paper presents an optimum design of a wide bandwidth, high-performance carbon nanotube field-effect transistor (CNFET) realization of a dual-output second-generation current conveyor (CCII±) at a 32-nm technology node. The performance of the CCII module has been thoroughly investigated in terms of number of carbon nanotubes (CNTs), the diameter of CNT and inter-CNT pitch. The parameters of individual CNFET are then modified to further improve the performance. The performance of the optimum CNFET (ITOPT)-based CCII is then compared with CMOS at different supply voltages. It has been found that CNFET-based CCII provides excellent high-frequency response and also consumes lower power at scaled supply voltage compared with its CMOS counterpart.

Variability analysis and FinFET-based design of XOR and XNOR circuit

Due to aggressive scaling and process imperfection in sub-45 nm technology node Vt (threshold voltage) shift is more pronounced causing large variations in circuit response. Therefore, this paper presents the analyses of various popular XOR/XNOR circuits in light of PVT (process, voltage and temperature) variations to verify their functionality and robustness. This paper first investigates output levels of various XOR/XNOR circuits. It further analyses those XOR/XNOR circuits offering better output levels in terms of delay and energy-delay product (EDP). It also performs variability analysis of those parameters to determine robustness of the XOR/XNOR designs. Finally, it implements the best XOR/XNOR circuit in emerging FinFET technology to achieve even better results in terms of propagation delay and EDP. The proposed FinFET-based implementation of XOR/XNOR circuit offers 1.4× improvement in delay and 1.8× improvement in EDP compared to its CMOS counterpart. It proves to be immune against process variation. It proves its robustness by offering 19.3× improvements in delay variability and 10.8× improvements in EDP variability.

Asterisk VoIP private branch exchange

This paper intends to present some important theoretical and practical results that we faced during setting up a VoIP (Voice over Internet Protocol) server with the well known open source VoIP server Asterisk. For a fully functional voice exchange we require to set up a server based on Asterisk, connecting clients to the server with the help of soft/hard phones and then comes the configuration aspects of the soft phones with the server. Here in our implementation we have connected the clients to the server with the help of SIP protocols.

Conferencing, Paging, Voice Mailing via Asterisk EPBX

This paper is intended to present theoretical and implementation details of various important features that are generally associated with an Asterisk based Voice Exchange i.e. Conferencing, Paging and Voice mailing. Besides this we will be concentrating on the web based approach for the configuration of the hard phones that will be used at the clients end. Our approach follows the client server model for all subsidiary procedures. The application is developed in C language and is compatible with all the versions of Linux, essentially providing PC to PC data and voice communications.

Robust subthreshold full adder design technique

This paper presents a technique to mitigate the impact of threshold voltage variation on digital circuit. The proposed technique increases logic depth by incorporating a transmission gate (TG) in the critical path of full adder architecture. It offers 1.04× improvement in EDP (energy-delay product) incurring 1.04× penalty in tp (propagation delay) at 350 mV with 200 fF CLoad (load capacitance) connected at SUM and CARRY outputs. It proves its robustness against process variations by offering 1.19× improvements in tp variability and 1.38× improvements in EDP variability. These improvements are achieved at the expense of two extra transistors used in a TG.

Energy Efficient and Process Tolerant Full Adder Design in Near Threshold Region Using FinFET

This paper investigates a robust 1-bit static full adder using FinFET at near-threshold region (NTR), a design space where the supply voltage is approximately equal to the threshold voltage of the transistors. This region provides minimum-energy point for the different frequency of operation with more favorable performance and variability characteristics. The proposed design features higher computing speed (by 4.49 x) and lower energy (by 3.90 x) at the expense of 1.13 x higher power dissipation. The proposed design also offers 1.38× improvements in power variability, 2.19× improvements in delay variability and 2.41× improvement in power delay product (PDP) variability against process, voltage, and temperature (PVT) variations. The power, speed and energy evaluation has been carried out using extensive simulation on HSPICE circuit simulator. The simulation results are based on 32nm Berkeley Predictive Technology Model (BPTM).

Performance optimization of CNFET based subthreshold circuits

Subthreshold circuits are an ideal choice for ultra low power, moderate throughput applications. In subthreshold region to meet the ultra-low power requirement of energy constrained devices, supply voltage less than the threshold voltage is applied. At same frequency, subthreshold circuits show orders of magnitude power saving over superthreshold circuits. In subthreshold operating region, minute leakage current is use as switching current but this limit the performance of logic gate. Primary goal while designing the subthreshold circuit is to increase the speed. Carbon Nano Tube Field Effect Transistors (CNFETs) is one of the most promising devices among emerging technologies. Most of the fundamental limitations of traditional MOSFETs are overcome in CNFETs. This paper investigates the performance analysis of subthreshold circuits and shown improvement in speed of logic gates using CNFETs. This paper primarily investigates the characteristics of CNFETs in subthreshold region. Improvement in performance of FO4, 1-bit full adder and 2:1 multiplexer is observed using CNFET over Si-MOSFET in subthreshold. This paper propose that reducing the gate oxide thickness of CNFET increases drive current and hence speeds with almost same amount of power dissipation.

Performance optimization of LUT of subthreshold FPGA in deep submicron

Field programmable gate array (FPGA) consumes significant dynamic and static power consumption due to the presence of additional logic for flexibility compared to application specific integrated circuits (ASICs). The cost of ASICs is rising exponentially in deep submicron and hence it is important to investigate ways of reducing FPGA power consumption so that they can also be employed in place of ASICs in portable energy constrained applications. It is also important to investigate the possibility of extending the use of FPGA even in subthreshold region for ultra low power applications. At the same frequency, subthreshold circuits show orders of magnitude power saving over super-threshold circuits for low throughput applications. This paper explores the subthreshold performance of a basic FPGA building block-a Look up Table (LUT). It presents comparative analysis of different topologies of three input LUT in deep submicron (DSM) for delay, power dissipation and switching energy. The proposed cross-coupled PMOS (CCP) encoded LUT shows 36% improvement in delay and 31% in switching energy at the cost of 4% increase in static power dissipation over conventional one. However, the increase in static power consumption is negligible compared to the improvement in switching energy. Thereafter, this paper investigates the potential of carbon nanotube field effect transistor (CNFET) based LUT in the subthreshold region.

Performance investigation of DG-FinFET for subthreshold applications

Subthreshold circuits have received widespread attention towards fulfilling ultralow power requirement of battery operated portable devices. Si-MOSFET shows huge performance degradation in terms of speed and robustness against variations when operated in subthreshold region. Improving the same will further expand their application area. DG FinFETs are most promising even in subthreshold region which overcomes most of the limitations of Si-MOSFET device. This paper investigates the effect of DG FinFET device parameters on the performance of 1-bit full adder cell and five stage ring oscillator. The work in this paper shows that by optimizing the fin and oxide thicknesses, the subthreshold performance of DG FinFET can be significantly improved. The effect of Process, Voltage, and Temperature (PVT) variation on robustness of circuit has been also explored under subthreshold conditions.