S. D. Pable

High speed interconnect through device optimization for subthreshold FPGA

Field programmable gate array (FPGA) consumes a significant amount of static and dynamic power due to the presence of additional logic for providing more flexibility as compared to application specific integrated circuits (ASICs). The fabrication cost of ASICs is rising exponentially in deep submicron and hence it is important to investigate different techniques for reducing FPGA power consumption so that they can also be employed in place of ASICs in portable energy constrained applications. It is also important to investigate the possibility of extending the use of FPGA even to subthreshold region for ultra low power (ULP) applications. Interconnect resources of an FPGA consumes most of the chip power, area and also determines the overall circuit delay. Subthreshold circuits show orders of magnitude power saving over superthreshold circuits. Improving the performance of subthreshold circuits is a main design challenge at the circuit and device levels to spread their application area. This paper proposes to improve the performance of subthreshold FPGA in terms of delay and switching energy by optimizing and operating interconnect drivers in the near threshold operating region. The possibility of inserting repeaters and the suitability of CNT as an interconnect in the subthreshold region are also explored. The simulation of FPGA interconnect resources using the proposed technique shows 67%, 73.33% and 61.8% increase in speed and 35.72%, 39% and 35.44% reduction in switching energy for Double, Hex and Long interconnect segments, respectively, over the conventional one.

Ultra-low-power signaling challenges for subthreshold global interconnects

Demand of power efficient circuits has grown significantly due to fast growth of battery operated portable applications. Though, subthreshold operation of device shows huge potential towards satisfying the ULP requirement, it holds many challenging design issues. As integration density of interconnect increases at every technology node, increased delay and crosstalk become more challenging design issues particularly for subthreshold interconnects. Nanometer subthreshold interconnect faces subthreshold driver design challenges and problems due to increased interconnect capacitance. This paper explored the suitability of different conventional interconnects strategies and challenges to reduce the total path delay. It also proposed device and interconnect optimization techniques to achieve higher performance and to reduce crosstalk in future subthreshold global interconnects. The effect of variability on subthreshold interconnects have also been investigated.

Interconnect optimization to enhance the performance of subthreshold circuits

Subthreshold circuits are shown to be the best candidate for satisfying the ultra-low power demand of battery-operated systems having moderate throughput. However, exponential increase in driver resistance in subthreshold region and increased global interconnect capacitance will become a major hurdle in improving the speed of subthreshold interconnects. Improving the speed of such low power circuits is a major design challenge in ultra low power domain. This paper presents a comprehensive analysis of Cu and mixed CNT bundle interconnects and investigates their performance in terms of delay and energy delay product (EDP) for future subthreshold circuits. This paper mainly contributes towards optimizing the geometrical (aspect ratio scaling) and process parameters of interconnects especially for subthreshold circuits to increase their speed. Crosstalk analysis has also been carried out with the proposed interconnect geometrical parameters. It has been found that aspect ratio scaling significantly reduces the interconnect delay and switching energy and at minimum aspect ratio, Cu wire performs better than even an optimized mixed CNT bundle for global interconnect length under subthreshold conditions.

A novel robust FPGA routing switch box design for ultra low power applications

Fabrication cost of application-specific integrated circuits (ASICs) is exponentially rising in deep submicron region due to rapidly rising non-recurring engineering cost. Field programmable gate arrays (FPGAs) provide an attractive alternative to ASICs but consume an order of magnitude higher power. There is a need to explore ways of reducing FPGA power consumption so that they can also be employed in ultra low power (ULP) applications instead of ASICs. Subthreshold region of operation is an ideal choice for ULP low-throughput FPGAs. The routing of an FPGA consumes most of the chip area and primarily determines the circuit delay and power consumption. There is a need to design moderate-speed ULP routing switches for subthreshold FPGA. This article proposes a novel subthreshold FPGA routing switch box (SB) that utilises the leakage voltage through transistor as biasing voltage which shows 69%, 61.2% and 30% improvement in delay, power delay product and delay variation, respectively, over conventional routing SB.

Performance optimization of CNFET based subthreshold circuits

Subthreshold circuits are an ideal choice for ultra low power, moderate throughput applications. In subthreshold region to meet the ultra-low power requirement of energy constrained devices, supply voltage less than the threshold voltage is applied. At same frequency, subthreshold circuits show orders of magnitude power saving over superthreshold circuits. In subthreshold operating region, minute leakage current is use as switching current but this limit the performance of logic gate. Primary goal while designing the subthreshold circuit is to increase the speed. Carbon Nano Tube Field Effect Transistors (CNFETs) is one of the most promising devices among emerging technologies. Most of the fundamental limitations of traditional MOSFETs are overcome in CNFETs. This paper investigates the performance analysis of subthreshold circuits and shown improvement in speed of logic gates using CNFETs. This paper primarily investigates the characteristics of CNFETs in subthreshold region. Improvement in performance of FO4, 1-bit full adder and 2:1 multiplexer is observed using CNFET over Si-MOSFET in subthreshold. This paper propose that reducing the gate oxide thickness of CNFET increases drive current and hence speeds with almost same amount of power dissipation.

Design of low power current starved VCO with improved frequency stability

Voltage Controlled Oscillator (VCO) plays a vital role in deciding the performance of VLSI circuits. Lot of research work is carried out on VCO from the past decades to achieve higher frequency, low power, low operating voltage, lower phase noise, and to increase tuning range. This paper mainly explores design of current starved voltage controlled ring oscillator for ultra low power applications. The performance comparison is done with respect to frequency stability and power consumption characteristics at 32nm technology node. Proposed C.S.D.T connection of VCO shows 48% higher speed at the cost of 18.9% increased power consumption over conventional VCO at VDD = 0.4V. Furthermore, this paper explores effect of temperature variations on VCO performance. Proposed VCO shows less sensitivity to temperature variation over conventional VCO.

Robustness comparison of emerging devices for portable applications

Extensive development in portable devices imposes pressing need for designing VLSI circuits with ultralow power (ULP) consumption. Subthreshold operating region is found to be an attractive solution for achieving ultralow power. However, it limits the circuit speed due to use of parasitic leakage current as drive current. Maintaining power dissipation at ultralow level with enhanced speed will further broaden the application area of subthreshold circuits even towards the field programmable gate arrays and real-time portable domain. Operating the Si-MOSFET in subthreshold regions degrades the circuit performance in terms of speed and also increases the well-designed circuit parameter spreading due to process, voltage, and temperature variations. This may cause the subthreshold circuit failure at very low supply voltage. It is essential to examine the robustness of most emerging devices against PVT variations. Therefore, this paper investigates and compares the performance of most promising upcoming devices like CNFET and DG FinFET in subthreshold regions. Effect of PVT variation on performance of CNFET and DG FinFET has been explored and it is found that CNFET is more robust than DG-FinFET under subthreshold conditions against PVT variations.

Performance optimization of LUT of subthreshold FPGA in deep submicron

Field programmable gate array (FPGA) consumes significant dynamic and static power consumption due to the presence of additional logic for flexibility compared to application specific integrated circuits (ASICs). The cost of ASICs is rising exponentially in deep submicron and hence it is important to investigate ways of reducing FPGA power consumption so that they can also be employed in place of ASICs in portable energy constrained applications. It is also important to investigate the possibility of extending the use of FPGA even in subthreshold region for ultra low power applications. At the same frequency, subthreshold circuits show orders of magnitude power saving over super-threshold circuits for low throughput applications. This paper explores the subthreshold performance of a basic FPGA building block-a Look up Table (LUT). It presents comparative analysis of different topologies of three input LUT in deep submicron (DSM) for delay, power dissipation and switching energy. The proposed cross-coupled PMOS (CCP) encoded LUT shows 36% improvement in delay and 31% in switching energy at the cost of 4% increase in static power dissipation over conventional one. However, the increase in static power consumption is negligible compared to the improvement in switching energy. Thereafter, this paper investigates the potential of carbon nanotube field effect transistor (CNFET) based LUT in the subthreshold region.

Implementation of a novel co-design of LVTSCR for effective ESD protection in ultra-deep submicron IC

As the technology is scaling downs day by day designing of radio frequency integrated circuit (RFICs) is introduces more challenges in the world of electronics. The challenges are such as area gain, size, and leakage current, electrostatic discharge (ESD), power consumptions & so many, raises the threat while designing the electronic circuitry. Among all these challenges we are focusing on the ESD-protection because of 70% of ICs are fails due to ESD happening. Reliability of ICs is one of the most important factor semiconductor industries. SD protection of RFIC is very challenging job due to lack of various ESD models & their proper communication with core circuit. Here a novel co-design methodology is suggested which is a simulation based process. In this technique a 130nm or 0.13μm CMOS technology is used & for ESD protection LVTSCR (Low Voltage Triggered Silicon Controlled Rectifier) is incorporated. The extracted results are compared. Such as without ESD protection (core circuit) & with ESD protection circuit (Protection +Core Circuit).The RF-ESD design of 5GHz to 6GHz LNA is used to show the implementation of this novel technique. A novel co-designed ESD protected LNA circuit achieves good on chip performance, including 4-kV ESD protection, a gain of 16.770 dB, noise figure 3.025 dB, input matching -8.454 dB, and output matching is -12.233 dB in same LNA-ESD protected design.

Performance investigation of DG-FinFET for subthreshold applications

Subthreshold circuits have received widespread attention towards fulfilling ultralow power requirement of battery operated portable devices. Si-MOSFET shows huge performance degradation in terms of speed and robustness against variations when operated in subthreshold region. Improving the same will further expand their application area. DG FinFETs are most promising even in subthreshold region which overcomes most of the limitations of Si-MOSFET device. This paper investigates the effect of DG FinFET device parameters on the performance of 1-bit full adder cell and five stage ring oscillator. The work in this paper shows that by optimizing the fin and oxide thicknesses, the subthreshold performance of DG FinFET can be significantly improved. The effect of Process, Voltage, and Temperature (PVT) variation on robustness of circuit has been also explored under subthreshold conditions.