Mohd. Hasan

Leakage Characterization of 10T SRAM Cell

This paper presents a technique for designing a low-power and variability-aware SRAM cell. The cell achieves low power dissipation due to its series-connected tail transistor and read buffers, which offer a stacking effect. This paper studies the impact of process, voltage, and temperature (PVT) variations on most of the design metrics of the SRAM cell and compares the results with standard 6T, 9T, and ST10T (Schmitt trigger based) SRAM cells.

A novel coefficient ordering based low power pipelined radix-4 FFT processor for wireless LAN applications

The FFT processor is a critical block in all multicarrier systems used primarily in the mobile environment. The portability requirement of these systems is mainly responsible for the need of low power FFT architectures. This paper proposes a technique to reduce the power consumption of a popular low power radix-4 pipelined FFT processor by modifying its operation sequence. The complex multiplier is one of the most power consuming blocks in the FFT processor. The switching activity at its fixed coefficient input, and hence its power consumption, can be drastically reduced by coefficient ordering. Coefficient ordering requires a novel commutator architecture which can handle the corresponding data sequencing as per new coefficient ordering. The resulting power saving is around 23% and 9%, respectively, for the 16-point and 64-point radix-4 pipelined FFT processor. This approach is very attractive for orthogonal frequency division multiplexing (OFDM) based wireless LAN (IEEE 802.11) requiring short FFTs but it can also be applied to the penultimate stage of longer FFTs used in digital audio and video broadcasting.

Performance comparison of CNFET- and CMOS-based 6T SRAM cell in deep submicron

This paper presents a performance comparison of a carbon nanotube-based field effect (CNFET)- and CMOS-based 6T SRAM cell at the 32nm technology node. HSPICE simulations, carried out using Berkeley predictive technology model (BPTM), show that for a cell ratio and pull-up ratio of 1, CNFET-based 6T SRAM cell provides an improvement of 21% in read static noise margin (SNM) at VDD=0.4V. The speed of CNFET cell is 1.84x that of CMOS cell. The standby leakage of CNFET cell is 84% less than CMOS cell. The process parameter variation results in 1.2% change in the read SNM of CNFET cell as compared with a wide variation of around 10.6% in CMOS cell.

Variability aware low leakage reliable SRAM cell design technique

This paper presents a technique for designing a low power SRAM cell. The cell achieves low power dissipation due to its series connected drivers driven by bitlines and read buffers which offer stack effect. The paper investigates the impact of process, voltage, and temperature (PVT) variations on standby leakage and finds appreciable improvement in power dissipation. It also estimates read/write delay, read stability, write-ability, and compares the results with that of standard 6T SRAM cell. The comparative study based on Monte Carlo simulation exhibits appreciable improvement in leakage power dissipation and other design metrics at the expense of 84% area overhead.

Optimized Design of a 32-nm CNFET-Based Low-Power Ultrawideband CCII

CMOS technology faces significant challenges like tunneling effect, random dopant fluctuation, and line edge roughness at channel lengths below 45 nm. Carbon nanotube-based electronics seems to be a better prospect for extending the saturating Moores law because of its higher mobility, scalability, and better channel electrostatics. This paper presents an optimum design of a wide bandwidth, high-performance carbon nanotube field-effect transistor (CNFET) realization of a dual-output second-generation current conveyor (CCII±) at a 32-nm technology node. The performance of the CCII module has been thoroughly investigated in terms of number of carbon nanotubes (CNTs), the diameter of CNT and inter-CNT pitch. The parameters of individual CNFET are then modified to further improve the performance. The performance of the optimum CNFET (ITOPT)-based CCII is then compared with CMOS at different supply voltages. It has been found that CNFET-based CCII provides excellent high-frequency response and also consumes lower power at scaled supply voltage compared with its CMOS counterpart.

Novel low power pipelined FFT based on subexpression sharing for wireless LAN applications

This paper proposes a novel low power multiplierless radix-4 single-path delay commutator (R4SDC) FFT processor architecture for wireless LAN (IEEE 802.11 standard) applications, where short FFT are utilised in the implementation of the physical layer. The multiplierless architecture uses shift and addition operations to realize complex multiplications. By combining a new commutator architecture, and low power butterfly architectures with this approach, the resulting power savings are around 19% and 35% for 64-point and 16-point radix-4 FFT respectively, as compared to a conventional FFT architecture based on non-Booth coded Wallace tree multiplier.

A delay spread based low power reconfigurable FFT processor architecture for wireless receiver

This paper proposes a novel concept of adjusting the FFT size in real time as per the delay spread in wireless receivers. The FFT size in OFDM/MC-CDMA based wireless receivers varies from 1024(1k)-point to 16-point. A low power reconfigurable radix-4 1k-point FFT processor architecture is proposed that can also be configured as a 256-point, 64-point or 16-point as per the channel parameters. By tailoring the clock of the higher FFT stages for longer FFTs, significant power saving is achieved by switching to shorter FFTs from longer FFTs.

Variation resilient subthreshold SRAM cell design technique

This article presents a circuit technique for designing a variability resilient subthreshold static random access memory (SRAM) cell. The architecture of the proposed cell is similar to the conventional 10T SRAM cell with the exception that dynamic threshold MOS is used for the read/write access FETs and cell content body bias scheme is used for bitline droppers (FETs used to drop bitlines). Moreover, the proposed bitcell utilises single differential port unlike conventional 10T bitcell which utilises dual differential ports. The proposed design offers 2.1× improvement in T RA (read access time) and 3.2× improvement in T WA (write access time) compared to CON10T at iso-device-area and 200 mV. It exhibits three roots in its read voltage transfer characteristic (VTC) even at 150 mV showing its ability to function as a bistable circuit. The combination of write and read VTCs for write static noise margin of the proposed design also shows single root signifying its write-ability even at 150 mV. It proves its robustness against process variations by featuring narrower spread in T RA distribution (by 1.3×) and in T WA distribution (by 1.2×) at 200 mV.

Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell

This paper presents a Schmitt-trigger-based single-ended 11T SRAM cell, which significantly improves read and write static noise margin (SNM) and consumes low power. Simulation results show that the cell also achieves the lowest leakage power dissipation among the cells considered for comparison. We also investigate the impact of process, voltage, and temperature variations on various performance parameters, such as hold SNM, read SNM, write margin, immunity to half-select issue, ION/IOFF ratio of read path, and leakage power of the cell; Monte Carlo simulation results confirm the robustness of the proposed cell toward these issues. Layout drawn in a 45-nm technology rule shows that the proposed cell occupies 2.02× greater area as compared with 6T SRAM cells. However, 6.9× higher ION/IOFF ratio of the read path of the proposed cell as compared with 6T cell holds potential to significantly subside the area overhead. A new figure of merit that comprehensively captures stability, delay, power dissipation, and area of an SRAM cell is also proposed. Based on the proposed metric, we observe that the proposed cell outperforms all, but one of the SRAM cells considered in this paper.

Multiplier-less based parallel-pipelined FFT architectures for wireless communication applications

This paper proposes two novel parallel-pipelined FFT architectures, based on multiplier-less implementation, targeting wireless communication applications, such as IEEE 802.11 wireless baseband chip and MC-CDMA receiver. The proposed parallel-pipelined architectures have the advantages of high throughput and high power efficiency. The multiplier-less architecture uses shift and addition operations to realize complex multiplications. By combining a new commutator architecture, and a low power butterfly with this approach, the resulting power and area savings are up to 31% and 20% respectively, for 64-point and 16-point FFTs, as compared to parallel-pipelined FFTs based on Booth coded Wallace tree multipliers.