Alek C. Chen

Development of layout split algorithms and printability evaluation for double patterning technology

When using the most advanced water-based immersion scanner at the 32nm node half-pitch, the image resolution will be below the k1 limit of 0.25. If EUV technology is not ready for mass production, double patterning technology (DPT) is one of the solutions to bridge the gap between wet ArF and EUV platforms. DPT technology implies a patterning process with two photolithography/etching steps. As a result, the critical pitch is reduced by a factor of 2, which means the k1 value could increase by a factor of 2. Due to the superimposition of patterns printed by two separate patterning steps, the overlay capability, in addition to image capability, contributes to critical dimension uniformity (CDU). The wafer throughput as well as cost is a concern because of the increased number of process steps. Therefore, the performance of imaging, overlay, and throughput of a scanner must be improved in order to implement DPT cost effectively. In addition, DPT requires an innovative software to evenly split the patterns into two layers for the full chip. Although current electronic design automation (EDA) tools can split the pattern through abundant geometry-manipulation functions, these functions, however, are insufficient. A rigorous pattern split requires more DPT-specific functions such as tagging/grouping critical features with two colors (and hence two layers), controlling the coloring sequence, correcting the printing error on stitching boundaries, dealing with color conflicts, increasing the coloring accuracy, considering full-chip possibility, etc. Therefore, in this paper we cover these issues by demonstrating a newly developed DPT pattern-split algorithm using a rule-based method. This method has one strong advantage of achieving very fast processing speed, so a full-chip DPT pattern split is practical. After the pattern split, all of the color conflicts are highlighted. Some of the color conflicts can be resolved by aggressive model-based methods, while the un-resolvable conflicts, known as native conflicts, require a change in the design to achieve a DPTfriendly design. A model-based stitching boundary correction is then used after the color conflicts are corrected. Finally the OPC treatment is implemented on both split layouts. The OPC challenges are highlighted by examining the printed image from both exposures. The key concepts described above with additional full chip requirements have been successfully implemented onto Brions TachyoTM system. The efficiency and accuracy of the DPT pattern split method were evaluated on a full-chip layout. The results show that the algorithm proposed in this paper is a viable solution for the DPT pattern split.

Fully model-based methodology for simultaneous correction of extreme ultraviolet mask shadowing and proximity effects

Extreme ultraviolet (EUV) lithography is a promising candidate for high-volume manufacturing at the 22-nm half-pitch node and beyond. EUV projection lithography systems need to rely on reflective optical elements and masks with oblique illumination for image formation. It leads to undesired effects such as pattern shift and horizontal-to-vertical critical dimension bias, which are generally reported as shadowing. Rule-based approaches proposed to compensate for shadowing include changing mask topography, introducing mask defocus, and biasing patterns differently at different slit positions. However, the electromagnetic interaction between the incident light and the mask topography with complicated geometric patterns, such as optical diffraction, not only causes shadowing but also induces proximity effects. This phenomenon cannot be easily taken into account by rule-based corrections and thus imposes a challenge on a partially model-based correction flow, the so-called combination of rule- and model-based corrections. A fully model-based correction flow, which integrates an in-house optical proximity correction algorithm with rigorous three-dimensional mask simulation, is proposed to simultaneously compensate for shadowing and proximity effects. Simulation results for practical circuit layouts indicate that the fully model-based correction flow significantly outperforms the partially model-based one in terms of correction accuracy, while the total run time is slightly increased.

Using intrafield high-order correction to achieve overlay requirement beyond sub-40nm node

Overlay requirements for semiconductor devices are getting more demanding as the design rule shrinks. According to ITRS expectation[1], on product overlay budget is less than 8nm for the DRAM 40nm technology node. In order to meet this requirement, all overlay error sources have to be analyzed and controlled which include systematic, random, even intrafield high order errors. In this paper, we studied the possibility of achieving <7nm overlay control in mass production by using CPE, Correction Per Exposure mode, and Intra-field high order correction (i-HOPC). CPE is one of the functions in GridMapper package, which is a method to apply correction for each exposure to compensate both systematic and random overlay errors. If the intra-field overlay shows a non-linear fingerprint, e.g. due to either wafer processing or reticle pattern placement errors, the intra-field High Order Process Correction(iHOPC) provided by ASML can be used to compensate for this error . We performed the experiments on an immersion tool which has the GridMapper functionality. In our experiment, the previous layer was exposed on a dry machine. The wet to dry matching represent a more realistic scanner usage in the fab enviroment. Thus, the results contained the additional contribution of immersion-to-dry matched machine overlay. Our test result shows that the overlay can be improved by 70%, and the mean+3sigma of full wafer measurement can achieve near the range of 6 to 5nm. In this paper we also discuss the capability of implementation of CPE in the mass production environment since CPE requires additional wafer mearurement to create the proper overlay correction.

The lithography technology for the 32 nm HP and beyond

When using the most advanced water-based immersion scanner at the 32nm node half-pitch, the image resolution will be below the k1 limit of 0.25. In this paper, we will explore the capability of using the double pattern technique (DPT) to extend the resolution capability of the water-based immersion lithography and examine the readiness of EUV to carry the lithography resolution capability beyond the 32 nm HP. The DPT, whether done in two litho and etch steps (LELE) or using the side wall spacer and sacrificial layer technique (SPT), will require significant improvement in CDU and overlay process control performance. We will report the experimental results in exploring the CDU and overlay performance of the LELE and the SPT options. We will also demonstrate the need to perform full field and full wafer process corrections to compensate for dual CDU populations and overlay entangled CDU variations. Furthermore, we will make an assessment of EUV readiness to further extend the lithography resolution capability beyond the 32 nm half-pitch.

EUV stochastic noise analysis and LCDU mitigation by etching on dense contact-hole array patterns

Experimental local CD uniformity (LCDU) of the dense contact-hole (CH) array pattern is statistically decomposed into stochastic noise, mask component, and metrology factor. Each component are compared quantitatively, and traced after etching to find how much improvement can be achieved by smoothing. Etch CDU gain factor is defined as the differential of etch CD by resist CD, and used to estimate etch CDU on resist CDU. Stochastic noise has influenced on not only LCDU but also local placement error (LPE) of each contact-hole. This LPE is also decomposed into its constituents in the same statistical way. As a result, stochastic noise is found to be the most dominant factor on LCDU and LPE. Etch LCDU is well expected by Etch Gain factor, but LPE seems to be kept same after etching. Fingerprints are derived from the repeating component and the boundary size for excluding proximity effect in analysis is investigated.

Progress in Extending Immersion Lithography for the 32 nm Node and Beyond

Optical lithography has met the challenge of the Semiconductor Industrys increasing resolution and the tighter overlay requirements by progressively: increasing the optics numerical aperture; shortening the illumination wavelength; and supporting low-k factor processing. This trend continued with the wavelength being shortened to 13 nm for extreme ultraviolet (EUV) lithography tools, and with numerical apertures increased to 1.35 for water-based immersion lithography tools. Currently, water-based, 193 nm, immersion tools are capable of printing at <40 nm (half pitch) resolutions with <6 nm overlay accuracy. For the next lithographic nodes, water-based immersion lithography will be used with double patterning techniques, and this will pushdown to below the 32 nm node. The major challenges for the exposure tools are the tightening of the specifications required with double pattering, while dealing with shrinking process windows. The specifications requirements include increased throughput, tighter overlay, and tighter critical dimension control. New high-speed systems are being developed at ASML to meet these requirements. This paper reviews the possibility of using double patterning to extend immersion lithography tools, beyond the 32 nm node while production EUV lithography is coming on line.

Improvement of lithography process by using a FlexRay illuminator for memory applications

As is well recognized, source mask optimization (SMO) is a highly effective means of extending the lifetime of a certain photolithography generation without an expensive upgrade to the next generation optical system. More than an academic theory, source optimization first found practical applications in the debut of the pixel-like programmable illuminator in 2009 for producing near freeform illumination. Based on programmed illumination, related studies have demonstrated a nearly identical optical performance to that generated by the conventionally adopted diffractive optical element (DOE) device without the prolonged manufacturing time and relatively high cost of stocking up various DOEs. By using a commercially available pixel-like programmable illuminator from ASML, i.e. the FlexRay, this study investigates the effectiveness of FlexRay in enhancing image contrast and common process window. Before wafer exposure, full SMO and source-only (SO) optimization are implemented by Tachyon SMO software to select the optimum illumination source. Wafer exposure is performed by ASML XT:1950i scanner equipped with a FlexRay illuminator on a critical layer of DRAM process with known hotspots of resist peeling. Pupil information is collected by a sensor embedded in the scanner to confirm the produced source shape against the programmed source and the optically simulated CD. When the FlexRay illuminator is used, experimental results indicate that lithography hotspots are eliminated and depth of focus is improved by as much as 50% in comparison with those from a traditional AERIAL illuminator. Regular focus-exposure matrix (FEM) and the subsequent critical defects scanning reveal that the common process window of the tight-pitched array and the periphery can be enhanced simultaneously with no hotspot identified. Therefore, a programmed source is undoubtedly invaluable in terms of additional manufacturing flexibility and lower cost of ownership when attempting to improve product yield in high volume production.

Development of automatic OPC treatment and layout decomposition for double dipole lithography for low-k1 imaging

To extend the application of current optical lithographic tools to next generation production technology, it is necessary to reduce the k1 factor in Rayleighs resolution equation. Double dipole lithography (DDL) is one of the candidates for a low-k1 imaging technique and it is a viable solution for 65- and 45-nm technology nodes. Because DDL takes has the advantage of extreme off-axis illumination of the dipole, the printing capability of small features as well as their through-pitch common process window can be enhanced. However, as a dipole illuminator gains the benefits of high contrast only for structures perpendicular to the dipole orientation, the original mask layout must be converted into horizontal and vertical components and printed in a double exposure. Throughput will be sacrificed due to the multiple exposures. Nevertheless, DDL mask manufacture is relatively simple compared to the production of the more complicated phase shift mask (PSM) and chromeless phase lithography (CPL). As regards an overlay issued from the separate image composition, several papers have shown the minor effect on pattern fidelity using the current ArF scanner. To split the design layout according to the pattern orientation, the double exposure scheme needs an automatic layout conversion algorithm. To integrate the H V conversion with model- and/or rule-based optical proximity corrections (OPCs), several approaches for pattern decomposition associated with OPC treatment have been suggested. In this paper we will go over the development of model- and rule-based OPC treatment and will focus on current technology for accurate model-based OPC development with empirical model calibration. Using the technique the lithographic performances such as pattern fidelity, process window as well as overlay error sensitivity will be demonstrated. We focus on a 65-nm technology node with k1 near 0.31. Based on the success of tool development and verification, the DDL with full-chip OPC-treated decomposition will become a mature low-k1 imaging solution.

Understanding of stochastic noise

Stochastic noise has strong impact on local variability such as LWR (Line Width Roughness), LCDU (Local Critical Dimension Uniformity) and LPE (Local Placement Error), and it is basically originated from the particle nature of photon. Statistical uncertainties of particles, same as the stochastic noises, can be analytically calculated by considering aerial image as a probability density function of photons. Contact-hole is the best pattern for counting its photon, so LCDU of contact-hole array is estimated and compared with experimental results. Among several possible statistical events from mask to resist pattern, three independent events of aerial image formation, photon absorption in resist, and chemical reaction including acid generation are considered to predict stochastic noise for both EUV (Extreme Ultra Violet) and ArF immersion lithography.

High-speed, full 3D feature metrology for litho monitoring, matching, and model calibration with scatterometry

We studied the potential of optical scatterometry to measure the full 3D profile of features representative to real circuit design topology. The features were selected and printed under conditions to improve the measurability of the features by scatterometry without any loss of information content for litho monitoring and control applications. The impact of the scatterometry recipe and settings was evaluated and optimal settings were determined. We have applied this strategy on a variety of structures and gathered results using the YieldStar angular reflection based scatterometer. The reported results show that we obtained effective decoupling of the measurement of the 3 dimensions of the features. The results match with predictions by calibrated lithographic simulations. As a verification we have successfully performed a scanner matching experiment using computational Pattern Matcher (cPM) in combination with YieldStar as a metrology tool to characterize the difference between the scanners and verify the matching. The results thus obtained were better than using CD-SEM for matching and verification.