Philip C. W. Ng

Fully model-based methodology for simultaneous correction of extreme ultraviolet mask shadowing and proximity effects

Extreme ultraviolet (EUV) lithography is a promising candidate for high-volume manufacturing at the 22-nm half-pitch node and beyond. EUV projection lithography systems need to rely on reflective optical elements and masks with oblique illumination for image formation. It leads to undesired effects such as pattern shift and horizontal-to-vertical critical dimension bias, which are generally reported as shadowing. Rule-based approaches proposed to compensate for shadowing include changing mask topography, introducing mask defocus, and biasing patterns differently at different slit positions. However, the electromagnetic interaction between the incident light and the mask topography with complicated geometric patterns, such as optical diffraction, not only causes shadowing but also induces proximity effects. This phenomenon cannot be easily taken into account by rule-based corrections and thus imposes a challenge on a partially model-based correction flow, the so-called combination of rule- and model-based corrections. A fully model-based correction flow, which integrates an in-house optical proximity correction algorithm with rigorous three-dimensional mask simulation, is proposed to simultaneously compensate for shadowing and proximity effects. Simulation results for practical circuit layouts indicate that the fully model-based correction flow significantly outperforms the partially model-based one in terms of correction accuracy, while the total run time is slightly increased.

A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects

Non-ideal pattern transfer from drawn circuit layout to manufactured nanometer transistors can severely affect electrical characteristics such as drive current, leakage current, and threshold voltage. Obtaining accurate electrical models of non-rectangular transistors due to sub-wavelength lithography effects is indispensable for DFM-aware nanometer IC design. In this paper, TCAD device simulations are utilized to quantify the accuracy of a standard equivalent gate length extraction approach for non-rectangular transistors. It is verified that threshold voltage and current density are non-uniform along the channel width due to narrow-width related edge effects, leading to significant inaccuracy in the sub-threshold region. A new EGL extraction method utilizing location-dependent weighting factors and convex parameter extraction techniques is proposed to account for the current density non-uniformity. Preliminary results verified by TCAD simulations indicate that the accuracy of leakage current estimation for non-rectangular transistors can be significantly improved. The method is readily applicable to calibration with real silicon data.

In situ beam drift detection using a two-dimensional electron-beam position monitoring system for multiple-electron-beam–direct-write lithography

Electron-beam lithography is one of the promising candidates to replace optical projection lithography due to its high resolution and maskless direct-write capability. In order to achieve the throughput requirement for high-volume manufacturing, miniaturized electro-optics elements are utilized to drive massively parallel beams simultaneously. In high-throughput multiple-electron-beam systems, beam positioning drift problems can become quite serious due to several factors such as thermal distortion and fabrication errors of electron optics. In single-beam systems, periodic recalibration with reference markers on the wafer can be utilized to achieve beam placement accuracy. This technique is not easy for multiple-beam systems. In this article, an innovative in situ two-dimensional electron-beam position monitoring system for multiple-electron-beam lithography is studied. An array of miniaturized electron detectors to measure scattered electrons from the substrate is placed above the wafer. It is assumed that the detector array signals are correlated with the distribution of electron trajectories, and the change of trajectory distortion due to the beam drift can be predicted by Monte Carlo electron-scattering simulation. A standard quadrant detection (SQD) method and a linear least-squares (LLS) method are used to estimate the beam drift from the detector array signals. Simulation results indicate that while the estimation uncertainty of both methods can be reduced substantially when the number of detected electrons is large enough. The LLS method always outperforms the SQD one regardless the detected electron numbers.

Model-based proximity effect correction for electron-beam direct-write lithography

A model-based proximity effect correction methodology is proposed and tested for electron-beam-direct-write lithography. It iteratively modulates layout geometry by feedback compensation until the correction error converges. The energy intensity distribution is efficiently calculated by fast convolving the modulated layout with a point-spread function which models electron beam shape and proximity effects primarily due to electron scattering in resist. The effectiveness of this methodology is measured by iteration numbers required for meeting the patterning fidelity specifications. It is examined versus process parameters including acceleration voltage and resist thickness with several regular mask geometries and practical design layouts.

A novel curve-fitting procedure for determining proximity effect parameters in electron beam lithography

Accelerating voltage as low as 5 kV for operation of the electron-beam micro-columns as well as solving the throughput problem is being considered for high-throughput direct-write lithography for the 22-nm half-pitch node and beyond. The development of efficient proximity effect correction (PEC) techniques at low-voltage is essential to the overall technology. For realization of this approach, a thorough understanding of electron scattering in solids, as well as precise data for fitting energy intensity distribution in the resist are needed. Although electron scattering has been intensively studied, we found that the conventional gradient based curve-fitting algorithms, merit functions, and performance index (PI) of the quality of the fit were not a well posed procedure from simulation results. Therefore, we proposed a new fitting procedure adopting a direct search fitting algorithm with a novel merit function. This procedure can effectively mitigate the difficulty of conventional gradient based curve-fitting algorithm. It is less sensitive to the choice of the trial parameters. It also avoids numerical problems and reduces fitting errors. We also proposed a new PI to better describe the quality of the fit than the conventional chi-square PI. An interesting result from applying the proposed procedure showed that the expression of absorbed electron energy density in 5keV cannot be well represented by conventional multi-Gaussian models. Preliminary simulation shows that a combination of a single Gaussian and double exponential functions can better represent low-voltage electron scattering.

Impacts of point spread function accuracy on patterning prediction and proximity effect correction in low-voltage electron-beam–direct-write lithography

Electron-beam–direct-write lithography at lower accelerating voltages has been considered as a candidate for next-generation lithography. Although long-range proximity effects are substantially reduced with the voltage, proximity effect correction (PEC) is still necessary since short-range proximity effects are relatively prominent. The effectiveness of model-based PEC can be limited severely if an inaccurate point spread function (PSF) characterizing electron scattering within resist is adopted. Recently, a new PSF form using a promising calibration method has been developed to more accurately characterize the electron scattering and thus significantly improve patterning fidelity at 5 keV. However, influences of adopting the conventional and new PSF forms for the usage of patterning practical circuit layouts have not been intensively studied. This work extensively investigates impacts of PSF accuracy on patterning prediction and PEC under different resist thickness conditions suitable for various lithogr...

Impacts of optical proximity correction settings on electrical performances

Due to non-ideal optical effects such as aberration and optical diffraction, printed poly gates on the wafer suffer from across-gate linewidth variation (AGLV) and across-chip linewidth variation (ACLV,) especially in the subwavelength regime. The poly gate distortion affects device electrical characteristics, including drive current (Ion), leakage current (Ioff), and threshold voltage (Vt). For circuits sensitive to layout, such as compact memory cells, electrical performances can vary with image distortion of each transistor even after applying resolution enhancement technologies (RETs) such as optical proximity corrections. In this paper, we demonstrate the impact of OPC settings on the performance of 6T-SRAM cells. The printed transistor gate and active region patterns are simulated by an in-house OPC engine. The device model for each distorted transistor is then extracted based on approximating each distorted channel pattern with a set of smaller rectangles. Consequently, Electrical performance such as static noise margin (SNM) can be obtained by incorporating these extracted device models into a circuit simulator. Preliminary results show that OPC settings such as segmentation length and numbers of corrections can affect wafer image quality and electrical performance in different ways.

Non-delta-chrome optical proximity correction methodology for process models with three-dimensional mask effects

As integrated circuit design dimensions continue to shrink, previously ignored three-dimensional (3-D) mask effects have become significant for the accurate prediction and correction of proximity effects. Optical proximity correction (OPC) process models must consequently take into account 3-D mask effects. The state-of-the-art model-based OPC methodology, which is called delta-chrome OPC (DCOPC), needs the repeated computation of the mask perturbation to facilitate its convergence. The increasing complexity of OPC process models challenges this DCOPC methodology because each computation of the mask perturbation becomes prohibitively expensive. In this study, a new model-based OPC methodology, which is called non-delta-chrome OPC (non-DCOPC), is proposed without introducing any mask perturbations. It only requires image intensity information to achieve convergence using classical control techniques, and its effectiveness is demonstrated, showing that the run time with and without considering 3-D mask effects can be significantly improved. In addition, the correction accuracy of the DCOPC and non-DCOPC methodologies without considering 3-D mask effects is quite comparable. However, the correction accuracy considering 3-D mask effects can be slightly improved by the non-DCOPC methodology.

Impact of Process-Effect Correction Strategies on Variability of Critical Dimension and Electrical Characteristics in Extreme Ultraviolet Lithography

The conventional correction strategy used to compensate for imaging errors in extreme ultraviolet (EUV) lithography is accomplished by incorporating independent corrections in which rule-based corrections are used to compensate for EUV-specific imaging effects such as mask shadowing, and a model-based correction is used to compensate for proximity effects. Because most rule-based corrections are empirically developed by using simple Manhattan patterns, some of the simplified approximation approaches would not be applicable in a circuit layout with complicated geometric patterns. These kinds of approximation approaches can lead to ineffective corrections of EUV-specific imaging effects, resulting in inaccurate patterns printed on a wafer which will significantly alter the electrical characteristics of fabricated circuits. In order to prevent the problems due to rule-based corrections, a promising correction strategy has been proposed to simultaneously deal with EUV-specific imaging effects and proximity effects. In this study, the impact of two different correction strategies on the critical dimension (CD) variation caused by defocus and the deviation of electrical characteristics from the design intent is explored. Numerical experiments indicate that the variability of CD and electrical characteristics is significantly improved by the proposed correction strategy.

New method of optimizing writing parameters in electron beam lithography systems for throughput improvement considering patterning fidelity constraints

Abstract. Low-energy electron beam lithography is one of the promising next-generation lithography technology solutions for the 21-nm half-pitch node and beyond because of fewer proximity effects, higher resist sensitivity, and less substrate damage compared with high-energy electron beam lithography. To achieve high-throughput manufacturing, low-energy electron beam lithography systems with writing parameters of larger beam size, larger grid size, and lower dosage are preferred. However, electron shot noise can significantly increase critical dimension deviation and line edge roughness. Its influence on patterning prediction accuracy becomes nonnegligible. To effectively maximize throughput while meeting patterning fidelity requirements according to the International Technology Roadmap for Semiconductors, a new method is proposed in this work that utilizes a new patterning prediction algorithm to rigorously characterize the patterning variability caused by the shot noise and a mathematical optimization algorithm to determine optimal writing parameters. The new patterning prediction algorithm can achieve a proper trade-off between computational effort and patterning prediction accuracy. Effectiveness of the new method is demonstrated on a static random-access memory circuit. The corresponding electrical performance is analyzed by using a gate-slicing technique and publicly available transistor models. Numerical results show that a significant improvement in the static noise margin can be achieved.