Aleksander Slusarczyk

Fast and compact sequential circuits through the information-driven circuit synthesis

Modern circuit implementation technologies (FPGAs, CPLDs, complex gates, etc.) introduce new implementation constraints and optimization criteria to sequential circuit synthesis. Moreover, to ensure good quality results, these criteria need to be applied throughout the entire circuit synthesis process, starting at state encoding. In this paper, we present new methods and tools for state encoding and combinational synthesis of sequential circuits based on new criteria of information flow optimization. Together they form a unified and complete pre-placement synthesis chain. Experimental results indicate that the unified, information-driven approach is effective, resulting in circuits from IWLS benchmark being on average 25% smaller and 30% faster than those synthesized by another state-of-the-art tools.

A new state assignment method targeting FPGA implementations

State assignment is one of the most important problems in hardware implementation of finite state machines. It influences to a high degree all quality aspects of the final hardware implementation. FPGAs are commonly used for implementation of systems produced in small- to medium-size series or requiring a relatively high speed and/or (re)programmability. With both speed and logic capacity rapidly growing, FPGAs evolved very quickly to highly-flexible technology of choice for major manufacturers. Unfortunately, the progress in synthesis methods and EDA tools for FPGA implementations does not keep up with the revolutionary development of the FPGA hardware platform. The characteristic features of the technology invalidate the traditionally used criteria, heuristics and synthesis methods. The development of new FPGA-targeted (near) optimal state assignment methods is therefore of primary practical importance. In this paper we propose a new state assignment method for FPGA implementations. It consists in optimization of the information flows in the resulting circuit. This results in binary functions with compact input supports, circuit composed of reasonably independent and highly coherent parts, and minimized (long) interconnections between the parts. The proposed method produces therefore compact and fast circuits in FPGA technology. Our tool that implements the method, compared to state-of-the-art encoding tools, consistently produces high quality results.

An effective solution of benchmarking problem: FSM benchmark generator and its application to analysis of state assignment methods

This paper focuses on the benchmarking that is one of the main issues of the synthesis method and tool development, analysis, characterization and evaluation. To solve several serious problems related to the usage of practical industrial benchmarks, we developed and implemented an FSM benchmark generator (BenGen). BenGen makes us possible to efficiently construct FSMs with various known characteristics, including FSMs representative to various typical industrial application areas, greatly reduces the necessity of having the actual industrial benchmarks, and enables research, comparison, evaluation and fine tuning of circuit synthesis methods largely independent of the industry, and much more effectively and efficiently than having only some industrial benchmarks. Using a large set of benchmarks generated with BenGen, we performed an experiment aiming at the effectiveness characterization of some popular academic and industrial FSM state assignment approaches. The experimental results enabled us among others to demonstrate that the pragmatic assignment approaches used commonly in todays commercial tools are only effective for some special classes of circuits or not effective at all.

Static Power Reduction in Nano CMOS Circuits Through an Adequate Circuit Synthesis

This paper addresses the power reduction issues in nano CMOS circuits, and focuses on the static-power and power-efficient circuit synthesis. It shows that the circuit synthesis approaches applied in todays commercial EDA-tools are not power-efficient in most cases, and experimentally demonstrates a high power-reduction potential of an adequate circuit synthesis. It also shows that our novel information-driven approach to circuit synthesis is able to robustly construct low-power circuits for the contemporary and future CMOS circuits.

Term Trees in Application to an Effective and Efficient ATPG for AND–EXOR and AND–OR Circuits

A compact data representation, in which the typically required operations are performed rapidly, and effective and efficient algorithms that work on these representations are the essential elements of a successful CAD tool. The objective of this paper is to present a new data representation—term trees (TTs)—and to discuss its application for an effective and efficient structural automatic test-pattern generation (ATPG). Term trees are decision diagrams similar to BDDs that are particularly suitable for structure representation of AND–OR and AND–EXOR circuits. In the paper, a flexible algorithm for minimum term-tree construction is discussed and an effective and efficient algorithm for ATPG for AND–EXOR and AND–OR circuits is proposed.

High-Quality Circuit Synthesis for Modern Technologies

Due to weaknesses in circuit synthesis methods used in todays CAD tools, the opportunities created by modern microelectronic technology cannot effectively be exploited. This paper considers the issues and requirements of circuit synthesis for the nano CMOS technologies, and discusses our new circuit synthesis technology that satisfies these requirements. The new technology considerably differs from all other known synthesis methods and overcomes their main weaknesses. The experimental results demonstrate that it produces very fast, compact and low-power circuits. The new technology has however many more major advantages that are discussed in the paper.

Multi-objective Optimal FSM State Assignment

The recent spectacular progress in modern microelectronics made possible implementation of a complex system on a single chip, and created a big stimulus towards development of embedded systems for the existing and new applications. Unfortunately, it also introduced unusual complexity that results in many serious issues that cannot be resolved without new more adequate multi-objective circuit and system development methods and EDA-tools. As a part of our research that aims at development of such more adequate methods, we performed a comparative analysis of several representative commercial and academic synthesis methods and tools for the FPGA-targeted FSM synthesis, and developed a new FPGA-targeted multi-objective FSM state assignment method. In this paper, a part of results and conclusions from our research is discussed

Interoperability and quality of new EDA tools for sequential logic synthesis

One of the main problems in design of modem microelectronic systems is achieving consistent high quality results along the entire EDA tool chain. Using the sequential logic synthesis tools for a case study, this paper shows how important is the consistent tool collaboration for the quality of the final result. In the paper, a new uniform and consistent information-driven logic synthesis approach is proposed and compared to some other logic synthesis flows, including the traditional flow involving JEDI and SIS. The experimental research demonstrates that the quality of the new information-driven logic synthesis tools and the harmony of the new uniform approach results in much better circuits than the circuits from all other flows. The information-based synthesis flow produced circuits that are on average 25% smaller and 30% faster than the circuits from traditional flow.