Artur Chojnacki

Fast and compact sequential circuits through the information-driven circuit synthesis

Modern circuit implementation technologies (FPGAs, CPLDs, complex gates, etc.) introduce new implementation constraints and optimization criteria to sequential circuit synthesis. Moreover, to ensure good quality results, these criteria need to be applied throughout the entire circuit synthesis process, starting at state encoding. In this paper, we present new methods and tools for state encoding and combinational synthesis of sequential circuits based on new criteria of information flow optimization. Together they form a unified and complete pre-placement synthesis chain. Experimental results indicate that the unified, information-driven approach is effective, resulting in circuits from IWLS benchmark being on average 25% smaller and 30% faster than those synthesized by another state-of-the-art tools.

High-quality sub-function construction in functional decomposition based on information relationship measures

Functional decomposition seems to be the most effective circuit synthesis approach for look-up table (LUT) FPGAs, (C)PLDs and complex gates. In the functional decomposition that targets LUT FPGAs, the circuit is constructed by recursively decomposing a given function and its sub-functions until each of the resulting sub-functions can be directly implemented with a LUT. The choice of sub-functions constructed in this process decides the quality of the resulting multi-level circuit expressed in terms of the logic block count and speed. In this paper, we propose a new effective and efficient method for the sub-function construction, and we consider its application in our circuit synthesis tool that targets LUT-based FPGAs. The method is based on the information relationship measures. The experimental results demonstrate that the proposed approach leads to extremely fast and very small circuits.

Multi-valued sub-function encoding in functional decomposition based on information relationships measures

Functional decomposition is becoming more and more popular, because it is more general than all other known logic synthesis approaches and it seems to be the most effective approach for LUT-based FPGAs, (C)PLDs and complex CMOS-gates. The multi-level functional decomposition can be seen as a recursive splitting of a given function, into two sub-functions: the predecessor (bound-set) function and successor function, initially, the bound set function is a multi-valued (symbolic) function, where a certain value (symbol) is assigned to each particular input-cube compatibility class of the function being decomposed. To be implemented with binary logic, the multi-valued bound-set function must be expressed as a set of binary functions. This transformation is called the multi-valued sub-function encoding. It can be performed by the binary code assignment to each particular input-cube compatibility class. It determines the resulting binary predecessor and successor sub-functions and therefore influences the quality of the resulting circuit to a high degree. In this paper, a new method of the multi-valued sub-function encoding is presented. The method is based on the information relationship measures. Experimental results from the prototype CAD-tool that implements the method demonstrate that it is able to efficiently construct extremely effective circuits for symmetric functions. Results for asymmetric functions are also very good.

Effective and efficient FPGA synthesis through functional decomposition based on information relationship measures

In this paper, a new information-driven circuit synthesis method is proposed that targets LUT-based FPGAs. The method is based on the bottom-up general functional decomposition and theory of information relationship measures that we previously developed. It differs considerably from all other known methods. The experimental results from the automatic circuit synthesis tool that implements the method clearly demonstrate that functional decomposition based on information relationship measures produces effective FPGA circuits.

Functional decomposition based on information relationship measures extremely effective for symmetric functions

In this paper, an original technology driven logic synthesis approach for look up table FPGAs and complex CMOS gates is presented. General functional decomposition, bottom-up construction and usage of the information relationships and measures are the key concepts of this approach. With this approach the technology mapping is trivial. The experimental results of the prototype tool that implements the approach are optimal for symmetric and are very promising for asymmetric functions.

Static Power Reduction in Nano CMOS Circuits Through an Adequate Circuit Synthesis

This paper addresses the power reduction issues in nano CMOS circuits, and focuses on the static-power and power-efficient circuit synthesis. It shows that the circuit synthesis approaches applied in todays commercial EDA-tools are not power-efficient in most cases, and experimentally demonstrates a high power-reduction potential of an adequate circuit synthesis. It also shows that our novel information-driven approach to circuit synthesis is able to robustly construct low-power circuits for the contemporary and future CMOS circuits.

High-quality FPGA designs through functional decomposition with sub-function input support selection based on information relationship measures

Functional decomposition seems to be the most effective circuit synthesis approach for look-up table (LUT) FPGAs, (C)PLDs and complex gates. Since LUT FPGAs are used in numerous important applications and constitute a foundation for the novel re-configurable system-on-a-chip platforms, an adequate synthesis for this target is of primary importance for the modern system industry. In the functional decomposition targeting LUT FPGAs, the circuit is constructed by recursively decomposing a given function and its sub-functions until each of the resulting sub-functions can be directly implemented with a LUT. The impact support selection for the sub-functions that are constructed in this process decides the quality of the resulting multi-level circuit to a high degree. In this paper; we propose a new effective method for the sub-function input support selection and discuss its application in our circuit synthesis tool that targets LUT-based FPGAs. The experimental results demonstrate that the proposed approach lends to extremely fast and very small circuits. The circuits consume on average over 2 times less logic blocks (CLBs) and are over 1.5 times faster than the circuits produced by the best state-of-the-art commercial tools.

Efficient logic synthesis for FPGAs with functional decomposition based on information relationship measures

General functional decomposition has important applications in many fields of modern engineering and science. Its practical usefulness for very complex systems is, however, limited by the lack of an effective and efficient method for selection of the appropriate input supports for subsystems. A classical method based on a systematic search of the whole solution space is inefficient. In this paper, an effective heuristic method for input support selection is proposed and discussed. The method is based on application of information relationship measures, which allows us to reduce the search space to a manageable size while keeping high-quality solutions in the reduced space. Experimental results demonstrate that the proposed heuristic method is able to construct optimal or near-optimal supports efficiently, even for large systems. It is much faster than the systematic method while delivering results of comparable quality.

High-Quality Circuit Synthesis for Modern Technologies

Due to weaknesses in circuit synthesis methods used in todays CAD tools, the opportunities created by modern microelectronic technology cannot effectively be exploited. This paper considers the issues and requirements of circuit synthesis for the nano CMOS technologies, and discusses our new circuit synthesis technology that satisfies these requirements. The new technology considerably differs from all other known synthesis methods and overcomes their main weaknesses. The experimental results demonstrate that it produces very fast, compact and low-power circuits. The new technology has however many more major advantages that are discussed in the paper.

Information-driven library-based circuit synthesis

The opportunities created by modern microelectronic technology cannot be effectively and efficiently exploited, because of weaknesses of the traditional circuit synthesis methods used in todays CAD tools. In this paper, a new information-driven circuit synthesis method is discussed that targets combinational circuits implemented with gates from the pre-characterized gate libraries. The method is based on our original information-driven approach to circuit synthesis, bottom-up general decomposition and theory of information relationship measures. It differs considerably from all other known methods. The experimental results from the automatic circuit synthesis tool that implements the method demonstrate that the information-driven general decomposition produces very fast and compact gate-based circuits.