Lech Józwiak

Decomposition of multiple-valued functions

This paper presents a generalized method for decomposition of multiple-valued functions. The main reason for using the described method is efficient implementation of logic circuits as well as effective representation of data in information systems. In logic synthesis, the method reduces the demand for silicon space required to implement designs. It is shown that the decomposition technique leads to additional compressing capabilities in PLA implementations. Another very promising area of application of decomposition is its effective representation of data in information systems, data bases and in other applications of information storing systems.

Information relationships and measures: an analysis apparatus for efficient information system synthesis

The analysis of information relationships is of primary importance for the analysis and synthesis of digital information systems. The paper aims to introduce and discuss the fundamental apparatus for the analysis and evaluation of information relationships. It defines and explains various relationships between information, measures for the amount and importance of information, and measures for the strength and importance of the information relationships. It demonstrates importance of the introduced relationships and measures for efficient synthesis, and shows how to apply them in the synthesis process. The analysis apparatus makes operational the famous theory of partitions and set systems of Hartmanis (1966). While partitions and set systems enable one to model information, the relationships and measures enable one to analyze and measure information and information relationships. Both together form a complete information modeling and analysis apparatus that can be applied in logic design, decision system design, pattern recognition, knowledge discovery, machine learning and other areas.

The influence of the number of values in sub-functions on the effectiveness and efficiency of the functional decomposition

General functional decomposition has important applications in many fields of modern engineering and science. However, its practical usefulness for very complex systems is limited by the lack of an effective and efficient method for the construction of high quality sub-systems. One of the three basic problems of sub-system construction is the choice of an appropriate multi-valued sub-function to be computed by a certain sub-system. In this paper we show that the number of values of the sub-function is the decisive factor in sub-function selection. It shows a very strong positive correlation with both the number of logic blocks and the number of logic levels in the decomposition network, i.e. with the cost and delay of the network. This is a very important result from the practical viewpoint, because its exploitation enables efficient construction of high-quality multi-level circuits, by selection of a sub-function with the minimum possible number of values at each decomposition step. This result also gives a link for the input support selection for sub-systems. The selected input support should enable construction of a sub-function with the minimum possible number of values.

An efficient approach to decomposition of multi-output Boolean functions with large sets of bound variables

Finding appropriate bound sets of variables is the most important task of functional decomposition. When solving some problems, the bound sets need to be larger, for instance in decomposition to symmetric subfunctions realized in MOPS arrays for submicron technologies, or when no good small bound sets exist. In such cases, the creation of the incompatibility graph, which is necessary to evaluate good variable partitionings, becomes very inefficient. Therefore, an algorithm is proposed that can speed up this process by orders of magnitude without sacrificing the quality of the decomposition, because the same graph coloring algorithms (exact or approximate) are still applied to the created graph.

Non-disjoint decomposition of Boolean functions and its application in FPGA-oriented technology mapping

We present a new theory of non-disjoint serial decomposition. We also present our new decomposition tool DEMAIN. The decomposition approach implemented in DEMAIN relies on: a partition-based representation of Boolean functions; and an effective balanced decomposition strategy that switches between the parallel and non-disjoint serial decomposition. In consequence, we applied the non-disjoint serial decomposition and parallel decomposition for efficient synthesis of FPGA-based circuits directed towards area or delay optimisation.

ASAM: Automatic architecture synthesis and application mapping

This paper focuses on mastering the automatic architecture synthesis and application mapping for heterogeneous massively-parallel MPSoCs based on customizable application-specific instruction-set processors (ASIPs). It presents an overview of the research being currently performed in the scope of the European project ASAM of the ARTEMIS program. The paper briefly presents the results of our analysis of the main challenges to be faced in the design of such heterogeneous MPSoCs. It explains which system, design, and electronic design automation (EDA) concepts seem to be adequate to address the challenges and solve the problems. Finally, it discusses the ASAM design-flow, its main stages and tools and their application to a real-life case study.

Information relationships and measures in application to logic design

In this paper, the theory of information relationships and relationship measures is considered and its application to logic design is discussed. This theory makes operational the famous theory of partitions and set systems of Hartmanis. The information relationships and measures enable us to analyze relationships between the modeled information streams and constitute an important analysis apparatus that can be used for analysis and synthesis of various information systems. It can be applied in logic design, pattern analysis, machine learning, and other fields. This paper shows how to apply the relationships and measures to logic design when using as examples three important problems: input support minimization, parallel decomposition and serial functional decomposition. The application examples and experimental results presented in the paper demonstrate the high potential of the information relationships and measures in solving logic synthesis problems.

Division-Based Versus General Decomposition-Based Multiple-Level Logic Synthesis

During the last decade, many different approaches have been proposed to solve the multiple-level synthesis problem with different minimum functionally complete systems of primitive logic blocks. The most popular of them is the division-based approach. However, modem microelectronic technology provides a large variety of building blocks which considerably differ from those typically considered. The traditional methods are therefore not suitable for synthesis with many modem building blocks. Furthermore, they often fail to find global optima for complex designs and leave unconsidered some important design aspects. Some of their weaknesses can be eliminated without leaving the paradigm they are based on, other ones are more fundamental. A paradigm which enables efficient exploitation of the opportunities created by the microelectronic technology is the general decomposition paradigm. The aim of this paper is to analyze and compare the general decomposition approach and the division-based approach. The most important advantages of the general decomposition approach are its generality (any network of any building blocks can be considered) and totality (all important design aspects can be considered) as well as handling the incompletely specified functions in a natural way. In many cases, the general decomposition approach gives much better results than the traditional approaches.

ASAM: Automatic Architecture Synthesis and Application Mapping

This paper focuses on mastering the automatic architecture synthesis and application mapping for heterogeneous massively-parallel MPSoCs based on customizable application-specific instruction-set processors (ASIPs). It presents an over-view of the research being currently performed in the scope of the European project ASAM of the ARTEMIS program. The paper briefly presents the results of our analysis of the main problems to be solved and challenges to be faced in the design of such heterogeneous MPSoCs. It explains which system, design, and electronic design automation (EDA) concepts seem to be adequate to resolve the problems and address the challenges. Finally, it introduces and briefly discusses the ASAM design-flow and its main stages.

Exploring processor parallelism: Estimation methods and optimization strategies

Former research on automatic exploration of ASIP architectures mostly focused on either the internal memory hierarchy, or the addition of complex custom operations to RISC based architectures. This paper focuses on VLIW architectures and, more specifically, on automating the selection of an application specific VLIW issue-width. An accurate and efficient issue-width estimation strongly influences all the important processor properties (e.g. processing speed, silicon area, and power consumption). We first compare different methods for estimating the required issue-width, and subsequently introduce a new force-based parallelism measure which is capable of estimating the required issue-width within 3% on average. Moreover, we show that we can quickly estimate the latency-parallelism Pareto-front of an example ECG application with less than 10% error using our issue-width estimations.