Alessandro Fin

SystemC: a homogenous environment to test embedded systems

The SystemC language is becoming a new standard in the EDA field and many designers are starting to use it to model complex systems. SystemC has been mainly adopted to define abstract models of hardware/software components, since they can be easily integrated for rapid prototyping. However, it can also be used to describe modules at a higher level of detail, e.g., RT-level hardware descriptions and assembly software modules. Thus, it would be possible to imagine a SystemC-based design flow, where the system description is translated from one abstraction level to the following one by always using SystemC representations. The adoption of a SystemC-based design flow would be particularly efficient for testing purpose as shown in this paper. In fact, it allows the definition of a homogeneous testing procedure, applicable to all design phases, based on the same error model and on the same test generation strategy. Moreover, test patterns are indifferently applied to hardware and software components, thus making the proposed testing methodology particularly suitable for embedded systems. Test patterns are generated on the SystemC description modeling the system at one abstraction level, then, they are used to validate the translation of the system to a lower abstraction level. New test patterns are then generated for the lower abstraction level to improve the quality of the test set and this process is iterated for each translation (synthesis) step.

AMLETO: a multi-language environment for functional test generation

More and more people are starting to use the SystemC description language to model and simulate new designs. This is due mainly to the simplicity and power of the language. The number of models written in SystemC currently available is still very limited and testing SystemC descriptions is still an open issue, since the language is new and researchers are looking for efficient error models and coverage metrics. This paper presents AMLETO, a multi-language environment developed to efficiently test embedded systems and IP-Cores. Using IIR, an HDL language independent representation, it supplies: fast translation from VHDL to SystemC of design descriptions and viceversa, generation and setup of customized TPGs for the design under test and generation of erroneous models capable of simulating the presence of design errors.

Functional test generation for behaviorally sequential models

Functional testing of HDL specifications is one of the most promising approaches for the verification of the functionalities of a design before synthesis. The contribution of this work is the development of a test generation algorithm targeting a new coverage metric (called bit-coverage) that provides full statement coverage, branch coverage, condition coverage and partial path coverage for behaviorally sequential models. The behavioral test sequences can be also the only way to evaluate testability of VHDL model for which a gate-level representation is not available (e.g third-party cores), since the behavioral error model is characterized also by a high correlation with the RT and gate-level stuck-at fault model. Moreover the preciseness of the proposed coverage metric makes the identified test sequences more effective in identifying design errors, than other test patterns developed by following standard coverage metrics.

A Web-CAD methodology for IP-core analysis and simulation

An effective selection of the more suited IP-core, available for a particular design, should be based on some simulation sessions. However, simulation models cannot be close enough to the real models of the core to protect the intellectual property. This paper proposes a Web-CAD methodology for IP-core analysis based on a client/server simulation architecture. The core vendor can make available to the public even the core models used for core synthesis without disclosing IP information. On the other side, the core user can simulate the remote core in the local simulation environment in the same way a local library component is simulated. To achieve this result, some problems concerning the non equivalence of the event driven semantic and the message driven semantic have been analyzed and solved.

A VHDL error simulator for functional test generation

This paper describes an efficient error simulator able to analyze functional VHDL descriptions. The proposed simulation environment can be based on commercial VHDL simulators. All components of the simulation environment are automatically built starting from the VHDL specification of the description under test. The effectiveness of the simulator has been measured by using a random functional test generator. Functional test patterns produce, on some benchmarks, a higher gate-level fault coverage than the fault coverage achieved by a very efficient gate-level test pattern generator. Moreover, functional test generation requires a fraction of the time necessary to generate test at the gate level. This is due to the possibility of effectively exploring the test patterns space since error simulation is directly performed at the VHDL level.

Laerte++: an object oriented high-level TPG for systemC designs

This paper describes Laerte++, a high-level test pattern generator (TPG) for SystemC designs. All necessary features of a high-level TPG (e.g., fault models definition, hierarchical analysis, coverage measurements, etc.) are implemented by exploiting native SystemC characteristics funded on OO principles. The framework robustness and extensibility are guaranteed by an accurate use of software engineering methodologies for the Larte++ classes definition and an extensive use of the Standard Template Library (STL) for data structure definition. Laerte++ allows to set up and run an ex-novo TPG session by adding very few C++ code lines to any SystemC design under test description. The applicability and the efficiency of the presented framework have been confirmed by the analyzed benchmarks.

Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG?

The paper examines the potentialities of genetic algorithms (GAs) with respect to the development of high-level TPGs. It summarizes at first the most relevant test pattern generation techniques based on genetic algorithms (GAs). This analysis distinguishes the considered techniques with respect to the abstraction level of the design under test. In particular, the effectiveness of gate-level GA-based TPGs is compared with the effectiveness of high-level GA-based TPGs. Differences are deeply investigated. They mainly concern the way genetic operators exploit specific simulation information to heuristically guide the genetic evolution. Moreover, a functional testing framework is described and used to actually measure on high-level descriptions the effectiveness of sophisticated GA-based TPGs in comparison to random approaches. Results are reported on a variety of benchmarks.

A genetic testing framework for digital integrated circuits

In order to reduce the time-to-market and simplify gate-level test generation for digital integrated circuits, GA-based functional test generation techniques are proposed for behavioral and register transfer level designs. The functional tests generated can be used for design verification, and they can also be reused at lower levels (i.e. register transfer and logic gate levels) for testability analysis and development. Experimental results demonstrate the effectiveness of the method in reducing the overall test generation time and increasing the gate-level fault coverage.

An application of genetic algorithms and BDDs to functional testing

This paper describes a functional level rest pattern generator, which combines two techniques: genetic algorithms (GAs) and binary decision diagrams (BDDs). The combined execution of such two techniques achieves better results for functional testing, than the single application of each separated technique. The entire set of functional errors is examined in a shorter time and a more compact test set is produced. The reason of this interesting result has been analyzed in the paper. It mainly depends on the fact that hard to detect errors for GA-based testing techniques are easy to detect than errors for BDD-based techniques and vice versa. The two testing approaches are thus complementary and can effectively cooperate.

A 1000X speed up for properties completeness evaluation

Verification of circuit description by means of model checking means to write propositions, expressed in some temporal logic, expected to be true on the implementation according to the specification content. Completeness of the set of written properties is still an open problem. We propose a practical approach to the property coverage metrics definition based on fault injection; a combination of model checking, fault simulation and emulation allows to reduce the coverage measure to an affordable task. The application of these three different technologies is illustrated on a real example, on which it leads to the discovery of a missing property in a property set formerly trusted to be complete.