Franco Fummi

SystemC cosimulation and emulation of multiprocessor SoC designs

SystemC is an open source C/C++ simulation environment that provides several class packages for specifying hardware blocks and communication channels. The design environment specifies software algorithmically as a set of functions embedded in abstract modules that communicate with one another and with hardware components via abstract communication channels. It enables transparent integration of instruction-set simulators and prototyping boards. The authors describe a simulation environment that targets heterogeneous multiprocessor systems. They are currently working to extend their methodology to more complex on-chip architectures.

Implicit test generation for behavioral VHDL models

This paper proposes a behavioral-level test pattern generation algorithm for behavioral VHDL descriptions. The proposed approach is based on the comparison between the implicit description of the fault-free behavior and the faulty behavior, obtained through a new behavioral fault model. The paper will experimentally show that the test patterns generated at the behavioral level provide a very high stuck-at fault coverage when applied to different gate-level implementations of the given VHDL behavioral specification. Gate-level ATPGs applied on these same circuits obtain lower fault coverage, in particular when considering circuits with hard to detect faults.

A SystemC-based framework for modeling and simulation of networked embedded systems

Next-generation networked embedded systems pose new challenges in the design and simulation domains. System design choices may affect the network behavior and network design choices may impact on the system design. For this reason, it is important -at the early stages of the design flow- to model and simulate not only the system under design, but also the heterogeneous networked environment in which it operates. For this purpose, we have exploited a modeling language traditionally used for System design -SystemC- to build a system/network simulator named SystemC Network Simulation Library (SCNSL). This library allows to model network scenarios in which different kinds of nodes, or nodes described at different abstraction levels, interact together. The use of SystemC as unique tool has the advantage that HW, SW, and network can be jointly designed, validated and refined. As a case study, the proposed tool has been used to simulate a sensor network application and it has been compared with NS-2, a well-known network simulator; SCNSL shows nearly two-order-magnitude speed up with TLM modeling and about the same performance as NS-2 with a mixed TLM/RTL scenario. The simulator is partially available to the community at http://sourceforge.net/projects/scnsl/.

Native ISS-SystemC integration for the co-simulation of multi-processor SoC

In a system-level design flow, the transition from a high-level description entry implies the refinement from an untimed, unpartitioned description to a real architecture where applications are executed on a programmable device and interact with ad-hoc hardware components. Simulation of such architectures requires the capability of efficient co-simulation of a model of hardware with a model of the processor. This paper presents two co-simulation methodologies, based on SystemC as hardware modeling language and on an instruction set simulator (ISS) as a model of the processor. The first one works at the SystemC kernel level and exploits potentialities of the GNU suite, whereas the second uses features offered by the operating system running on the ISS. The two methodologies improve co-simulation performance with respect to state-of the art methods, and provide different trade-offs between the simplicity of the programming model, the modeling power, and co-simulation performance.

A mutation model for the SystemC TLM 2.0 communication interfaces

Mutation analysis is a widely-adopted strategy in software testing with two main purposes: measuring the quality of test suites, and identifying redundant code in programs. Similar approaches are applied in hardware verification and testing too, especially at RTL or gate level, where mutants are generally referred as faults, and mutation analysis is performed by means of fault modeling and fault simulation. However, in modern embedded systems there is a close integration between HW and SW parts, and verification strategies should be applied early in the design flow. This requires the definition of new mutation analysis-based strategies that work at system level, where HW and SW functionalities are not partitioned yet. In this context, the paper proposes a mutation model for perturbing transaction level modeling (TLM) SystemC descriptions. In particular, the main constructs provided by the SystemC TLM 2.0 library have been analyzed, and a set of mutants is proposed to perturb the primitives related to the TLM communication interfaces.

SystemC: a homogenous environment to test embedded systems

The SystemC language is becoming a new standard in the EDA field and many designers are starting to use it to model complex systems. SystemC has been mainly adopted to define abstract models of hardware/software components, since they can be easily integrated for rapid prototyping. However, it can also be used to describe modules at a higher level of detail, e.g., RT-level hardware descriptions and assembly software modules. Thus, it would be possible to imagine a SystemC-based design flow, where the system description is translated from one abstraction level to the following one by always using SystemC representations. The adoption of a SystemC-based design flow would be particularly efficient for testing purpose as shown in this paper. In fact, it allows the definition of a homogeneous testing procedure, applicable to all design phases, based on the same error model and on the same test generation strategy. Moreover, test patterns are indifferently applied to hardware and software components, thus making the proposed testing methodology particularly suitable for embedded systems. Test patterns are generated on the SystemC description modeling the system at one abstraction level, then, they are used to validate the translation of the system to a lower abstraction level. New test patterns are then generated for the lower abstraction level to improve the quality of the test set and this process is iterated for each translation (synthesis) step.

Symbolic functional vector generation for VHDL specifications

Verification of the functional correctness of VHDL specifications is one of the primary and most time consuming tasks of design. However, it must necessarily be an incomplete task since it is impossible to completely exercise the specification by exhaustively applying all input patterns. The paper aims at presenting a two-step strategy based on symbolic analysis of the VHDL specification, using a behavioral fault model. First, we generate a reduced number of functional test vectors for each process of the specification which allows complete code statement coverage and bit coverage, allowing the identification of possible redundancies in the VHDL process. Then, through the definition of a controllability measure, we verify if these functional test vectors can be applied to the process inputs when interconnected to other processes. If this is not the case, the analysis of the nonapplicable inputs provides identification of possible code redundancies and design errors. Experimental results show that bit coverage provides complete statement coverage and a more detailed identification of possible design errors.

AMLETO: a multi-language environment for functional test generation

More and more people are starting to use the SystemC description language to model and simulate new designs. This is due mainly to the simplicity and power of the language. The number of models written in SystemC currently available is still very limited and testing SystemC descriptions is still an open issue, since the language is new and researchers are looking for efficient error models and coverage metrics. This paper presents AMLETO, a multi-language environment developed to efficiently test embedded systems and IP-Cores. Using IIR, an HDL language independent representation, it supplies: fast translation from VHDL to SystemC of design descriptions and viceversa, generation and setup of customized TPGs for the design under test and generation of erroneous models capable of simulating the presence of design errors.

Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions

Transaction-level modeling (TLM) is the most promising technique to deal with the increasing complexity of modern embedded systems. However, modeling a complex system completely at transaction level could be inconvenient when IP cores are available on the market, since they are usually modeled at register transfer level (RTL). In this context, modeling and verification methodologies based on transactors allow designers to reuse RTL IPs into TLM-RTL mixed designs, thus guaranteeing a considerable saving of time. Practical advantages of such an approach are evident, but mixed TLM-RTL designs cannot completely provide the well-known effectiveness in terms of simulation speed provided by TLM. This paper presents a methodology to automatically abstract RTL IPs into equivalent TLM descriptions. To do that, the paper first proposes a formal definition of equivalence based on events, showing how such a definition can be applied to prove the correctness of a code manipulation methodology, such as code abstraction. Then, the paper proposes a technique to automatically abstract RTL IPs into TLM descriptions. Finally, the paper shows that the TLM descriptions obtained by applying the proposed technique are correct by construction, relying on the given definition of event-based equivalence. A set of experimental results is reported to confirm the effectiveness of the methodology.

A timing-accurate modeling and simulation environment for networked embedded systems

The design of state-of-the-art, complex embedded system requires the capability of modeling and simulating the complex networked environment in which such systems operate. This implies the availability of both a networking modeling environment and traditional system-level modeling and simulation methodology based on a timing accurate integration of a system-level modeling language (SystemC) and a network simulation environment (NS-2). The efficiency of the proposed design environment has been demonstrated on a description of an 802.11 MAC layer.