Alessandro Manstretta

Mixed serial–parallel sensing scheme for a 64-Mbit 4-bit/cell factory-programmed OTP-ROM

Abstract This article presents a sensing scheme for multilevel (ML) non-volatile memories. Sensing is accomplished following a mixed serial–parallel approach: a memory cell is read according to a binary-search algorithm where each search step carries out a given number of simultaneous comparisons between its content and adequate references. Two sensing steps, each performing three parallel comparisons, are able to detect as many as 4 bits per cell (16 levels). Only three sense amplifiers are required per each cell to be read simultaneously. To obtain tight current distributions (within 3xa0μA) for the programmed states, as required for safely storing and sensing 4 bits per cell, a highly-parallel ML factory-programming technique for one-time programmable ROMs is used. Simulated access time for a 16-level-cell 64-Mbit device in a mature double-poly single-metal 0.4xa0μm CMOS EPROM technology is ∼120xa0ns when using 3xa0V power supply.