Roberto Gastaldi

A Multi-Level-Cell Bipolar-Selected Phase-Change Memory

Phase-change memory (PCM) is becoming widely recognized as the most likely candidate to unify the many memory technologies that exist today (Lee, et al., 2007). The combination of non-volatile attributes of flash, RAM-like bit-alterability, and fast reads and writes position PCM to enable changes in the memory subsystems of cellular phones, PCs and countless embedded and consumer electronics applications. This designs multi-level cell (MLC) capabilities combined with long- term scalability reduce PCM costs as only realized before by hard disk drives. MLC technology is challenged with fitting more cell states (4 in the case of 2 bit per cell), along with distribution spreads due to process, design, and environmental variations, within a limited window. We describe a 256Mb MLC test-chip in a 90nm micro-trench (mutrench) PCM technology, and MLC endurance results from an 8Mb 0.18mum PCM test-chip with the same trench cell structure. A program algorithm achieving tightly placed inner states and experimental results illustrating distinct current distributions are presented to demonstrate MLC capability.

Dichotomic current-mode serial sensing methodology for multistorage non-volatile memories

A serial sensing method for multistorage non-volatile memories, based on a dichotomic algorithm, is presented. While incorporating the main advantage of the serial approach (the use of a single sense amplifier), this method reduces sensing time to a minimum and ensures its independence from memory cell contents. Moreover, high throughput is ensured in serial-output memories.

Positive and negative CMOS voltage multiplier for 5-V-only flash memories

In this paper we present a circuit scheme capable of providing the supply voltage for the final stages of the row decoder in a 5-V-only flash memory. The circuit is capable of delivering the positive (5 V or 10.5 V) or negative (-12 V) voltage required in read, program and erase operations, respectively. The high positive and the negative voltages are obtained with voltage multipliers based on the charge-pump approach. A single line is used to supply the final stages of the row decoder. The topology proposed is suitable for single-well processes.