Pier Luigi Rolandi

A dynamically adaptive DSP for heterogeneous reconfigurable platforms

This paper describes a digital signal processor based on a multi-context, dynamically reconfigurable datapath, suitable for inclusion as an IP-block in complex SoC design projects. The IP was realized in CMOS 090 nm technology. The most relevant features offered by the proposed architecture with respect to state of the art are zero overhead for switching between successive configurations, relevant area and energy computational density on computational kernels (average of 2 GOPS/mm2, 0.2GOPS/mW) and relatively small area occupation (18 mm2), making it suitable for acceleration or upgrade of multi-core heterogeneous embedded platforms. The processor is delivered with a software tool chain providing the application developer algorithmic analysis and design space exploration based on ANSI C, with no utilization of hardware-related constructs or description languages

A 1.2-to-8V Charge-Pump with Improved Power Efficiency for Non-Volatille Memories

A charge-pump architecture is presented with an improved power efficiency and a high voltage output compared to the known Dickson and Favrat architectures due to partial reuse of the charge stored on the capacitors. An 8-stage charge pump fabricated in a 0.13mum CMOS process has a 1.2V supply and a 100MHz clock. The measured performance indicates that the efficiency can be 25% higher than a Favrat cell. The efficiency increases with the number of stages, reaching 60% with 10 stages.

Ultra-low-power analog associative memory core using flash-EEPROM-based programmable capacitors

Analog techniques can lead to ultra-efficient computational systems when applied to the right applications. The problem of associative memory is well suited to array-based analog implementation. The architectures which result can be ultra efficient both in terms of high density and low power consumption. We have implemented a small (16x512) analog associative memory array which uses programmable nonlinear capacitors based on flash EEPROM technology for both analog storage and analog Manhattan Distance computation. The core circuit involved is based on only two of these novel devices. Preliminary results from this test circuit indicate that we can achieve a computing precision of more than 8 digitalequivalent bits in a chip which is capable of performing 128 Giga absolute-value-of-difference-accumulate operations per second at a power consumption of less than 150 mW. Performance of this level is more than an order of magnitude more efficient than the best low-power digital techniques and demonstrates the potential advantages analog implementation has to offer when applied to certain applications. Introduction Associative Memory The function of an associative memory, or contentaddressable memory, is more or less the inverse of that of a random access memory: when presented with a partial or complete data vector, the memory should return the row address of the internally stored data vector which best “matches” the input data vector. The matching function is typically a distance function; in standard digital implementations Hamming distance is usually used. Associative memory lends itself to array-based parallel implementation. A typical architecture consists of a 2dimensional distance-computing / memory array, and several 1-dimensional arrays including an accumulator array for accumulating distances, a comparator array for finding the smallest distance, a priority encoder array for selecting rows one at a time, and a ROM array for presenting outputs [5]. * This work has been partially sponsored by U. C. Berkeley where Mr. Kramer is completing a Ph.D. Analog Associative Memory We are exploring an analog implementation of this ype of architecture for Associative Memory. The result is an analog associative memory in which both stored memory rows and inputs consist of analog-valued vectors (5-bit equivalent precision). The goal is to achieve an ultraefficient design in terms of both density and power consumption. Our target is an associative memory containing 4K lines of 64-dimensional memory vectors and capable of performing nearest neighbor match based on Manhattan Distance in less than 2uS at a power consumption of less than 150mW. Computation of 4K 64-dimensional Manhattan Distances requires 256K 5-bit absolute-value-of-differenceaccumulate computations, thus achieving a cycle time of 2uS requires performing 128G of these operations per second. Performing this much computation on a single chip at a power consumption of less than 150mW represents an increase in efficiency both in terms of density and power consumption of more than an order of magnitude over the best low-power digital techniques [1]. Practical realization of computing systems based on analog techniques may provide a viable alternative for ultraefficient system design if the design generality lost can be justified by the added efficiency gained.

System on chip with 1.12mW-32Gb/s AC-coupled 3D memory interface

An AC-coupled 3D memory interface for chip-to-chip communication is implemented in 90nm CMOS technology. It transfers 128 bit words between stacked SRAMs in an ARM-based System on Chip (SoC) platform at 250MHz. This interface requires 0.05mm2 of occupation area and achieves a 32Gbit/sec of throughput and an average energy consumption of 35µW/Gbit/sec.

A 1.2V-5V High Efficiency CMOS Charge Pump for Non-Volatile Memories

A new charge pump circuit is presented: it is based on PMOS pass transistors with dynamic control of the gate and body voltages. By controlling the gate and the bulk of each pass-transistor, the voltage loss due to the device threshold is removed and the charge is pumped from one stage to the other with negligible voltage drop. Compared to conventional charge pumps, it exhibits a larger output voltage and better power efficiency still retaining a simple two-phase clocking scheme. The architecture is based on low-voltage transistors and the voltage drop among the device terminals does not exceed the supply voltage. Measurements performed on a 4-stage charge pump, fabricated exploiting a ST 130nm CMOS process, are provided.

Words recognition using associative memory

Introduces the application of an analog associative memory chip to word recognition, which is a fundamental topic of the text recognition process. The word recognition method takes advantage of a statistical evaluation of the behavior of the optical character recognition system preceding it. That statistical information leads to the creation of a coding that is used to store a lexicon of the most used words in the chip. An input pattern is matched against the full database of the associative memory, and a set of closest patterns is returned. The precision reached by this operation ranges from 93% to 99%. These encouraging results demonstrate the general aptitude of the chip to solve classes of problems that need to use an associative memory.

An analog associative memory chip for VQ image compression

This paper presents a hardware implementation of full-search vector quantization image compression using an associative memory chip based on analog flash technology. Taking advantage of the features of this architecture, that performs a parallel search on 4 K 64-elements codebook in 4.6 /spl mu/s, encouraging results have been obtained in terms of perceived image quality and computation speed.

A Flash technology programmable non-volatile switch

A modified Flash-EEPROM device is presented. This device operates as a non-volatile programmable pass transistor. Program and erase, operations are performed on a Flash-EEPROM cell coupled to a pass-transistor. Written and erased states of the flash cell correspond to the open and close states of the pass-transistor respectively. The Flash-programmable pass transistor (FPT) was developed for multi-context programmable-logic, and it was realized in a technology for embedded Flash-EEPROM NOR memory. No additional process steps are required. This novel device has the same program and erasing behavior as the standard Flash-EEPROM cell, measurements are reported for a 0.18 /spl mu/m technology implementation.