Alessandro Paccagnella

A New Hardware/Software Platform and a New 1/E Neutron Source for Soft Error Studies: Testing FPGAs at the ISIS Facility

We introduce a new hardware/software platform for testing SRAM-based FPGAs under heavy-ion and neutron beams, capable of tracing the bit-flips in the configuration memory back to the physical resources affected in the FPGA. The validation was performed using, for the first time, the neutron source at the RAL-ISIS facility. The ISIS beam features a 1/E spectrum, which is similar to the terrestrial one with an acceleration between 107 and 108 in the energy range 10-100 MeV. The results gathered on Xilinx SRAM-based FPGAs are discussed in terms of cross section and circuit-level modifications.

Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA

This paper analyses the effects of single event upsets in an SRAM-based FPGA, with special emphasis for the transient faults affecting the configuration memory. Two approaches are combined: from one side, by exploiting the available information and tools dealing with the device configuration memory, we were able to make hypothesis on the meaning of every bit in the configuration memory. From the other side, radiation testing was exploited to validate the hypothesis and to gather experimental evidence about the correctness of the obtained results. As a major result, we can provide detailed information about the effects of SEUs affecting the configuration memory of a commercial FPGA device. As a second contribution, we describe a method for obtaining the same result with similar devices. Finally, the obtained results are crucial to allow the possible usage of SRAM-based FPGAs in safety-critical environments, e.g., by working on the place and route strategies of the supporting tools.

Radiation effects on floating-gate memory cells

We have addressed the problem of threshold voltage (V/sub TH/) variation in flash memory cells after heavy-ion irradiation by using specially designed array structures and test instruments. After irradiation, low V/sub TH/ tails appear in V/sub TH/ distributions, growing with ion linear energy transfer (LET) and fluence. In particular, high LET ions, such as iodine used in this paper, can produce a bit flip. Since the existing models cannot account for large charge losses from the floating gate, we propose a new mechanism, based on the excess of positive charge produced by a single ion, temporarily lowering the tunnel oxide barrier (positive charge assisted leakage current) and enhancing the tunneling current. This mechanism fully explains the experimental data we present.

Errata to “Identification and Classification of Single-Event Upsets in the Configuration Memory of SRAM-Based FPGAs”

This paper presents the radiation testing of a commercial-off-the-shelf SRAM-based field-programmable gate arrays (FPGAs) with heavy ions. Test experiments have been conducted to identify and to classify the single-event upsets (SEUs) in the configuration memory that induce single-event functional interrupt for the user-implemented circuit. Moreover the paper presents a new approach for assessing the effects of SEUs based on the combination of radiation testing and simulation-based fault injection tool. First experimental results show the FPGA look-up table (LUT) resources (used to implement combinatorial logic) are the most sensitive to SEUs, whereas interconnect resources are the most critical for the device cross section because they use the largest number of configuration bits. The analysis of experimental data underlines that the most probable error affecting interconnections is the shorting of two nets. This observation indicates that new fault models should be considered along with the classic stuck-at one model designing fault-tolerant architectures, which are intended for implementation in FPGA devices.

Impact ionization and light emission in AlGaAs/GaAs HEMT's

Impact ionization and light emission phenomena have been studied in AlGaAs/GaAs HEMTs biased at high drain voltages by measuring the gate excess current due to holes generated by impact ionization and by analyzing the energy distribution of the light emitted from devices in the 1.1-3.1 eV energy range. The emitted spectra in this energy range can be divided into three energy regions: (i) around 1.4 eV light emission is dominated by band-to-band recombination between cold electrons and holes in GaAs; (ii) in the energy range from 1.5 to 2.6 eV energy distribution of the emitted photons is approximately Maxwellian; and (iii) beyond 2.6 eV the spectra are markedly distorted due to light absorption in the n/sup +/ GaAs cap layer. The integrated intensity of photons with energies larger than 1.7 eV is proportional to the product of the drain and gate currents. This suggests recombination of channel electrons with holes generated by impact ionization as the dominant emission mechanism of visible light. >

Simulation-based analysis of SEU effects in SRAM-based FPGAs

SRAM-based field programmable gate arrays (FPGAs) are particularly sensitive to single event upsets (SEUs) that, by changing the FPGAs configuration memory, may affect dramatically the functions implemented by the device. In This work we describe a new approach for predicting SEU effects in circuits mapped on SRAM-based FPGAs that combines radiation testing with simulation. The former is used to characterize (in terms of device cross section) the technology on which the FPGA device is based, no matter which circuit it implements. The latter is used to predict the probability for a SEU to alter the expect behavior of a given circuit. By combining the two figures, we then compute the cross section of the circuit mapped on the pre-characterized device. Experimental results are presented that compare the approach we developed with a traditional one based on radiation testing only, to measure the cross section of a circuit mapped on an FPGA. The figures here reported confirm the accuracy of our approach.

Impact ionization, recombination, and visible light emission in AlGaAs/GaAs high electron mobility transistorsa)

This communication describes a detailed experimental investigation of light emitted from AlGaAs/GaAs high electron mobility transistors biased at high drain voltages where impact ionization occurs. We present the electroluminescence spectra in 1.1–3.1 eV energy range. The strong correlation of the integrated intensity of photons with hν≳1.7 eV with the product of hole current generated by impact ionization and of electron current indicates that the recombination process is the main mechanism for visible light emission.

Facility for fast neutron irradiation tests of electronics at the ISIS spallation neutron source

The VESUVIO beam line at the ISIS spallation neutron source was set up for neutron irradiation tests in the neutron energy range above 10MeV. The neutron flux and energy spectrum were shown, in benchmark activation measurements, to provide a neutron spectrum similar to the ambient one at sea level, but with an enhancement in intensity of a factor of 107. Such conditions are suitable for accelerated testing of electronic components, as was demonstrated here by measurements of soft error rates in recent technology field programable gate arrays.

A model for TID effects on floating Gate Memory cells

Four different technologies of floating gate (FG) memory arrays were subjected to /sup 60/Co gamma-rays and 10 keV X-rays irradiation to evaluate their response to the total ionizing dose. The effect of irradiation was a uniform charge loss across the whole array. Irradiation effects can be modeled as the result of two phenomena, namely, the generation of charge in the dielectric layers surrounding the floating gate and its subsequent recombination and drift, and the photoemission of carriers from the charged FG. The second phenomenon is effective at high doses. As a consequence of these two phenomena, devices featuring a smaller FG are less prone to total ionizing dose effects than devices featuring a larger FG, proper of older technological generations. We propose a model that accurately fits experimental data over a broad series of experimental conditions.

Aspect ratio calculation in n-channel MOSFETs with a gate-enclosed layout

Abstract Transistors with gate-enclosed layout can be used in radiation environments to prevent the onset of any leakage current through a radiation induced lateral path under the birds beak or at the shallow trench corner. The gate-enclosed layout introduces a non-standard device geometry and its effect on the MOSFET characteristics has been investigated here. In particular, we have addressed the problem of evaluating the MOSFET aspect ratio for selected gate-enclosed shapes. To this purpose, we have developed different analytical models in order to evaluate analytically the drain current expression at a low drain bias. The simplest model has been proposed for the circular devices, derived from a solution of the corresponding problem featuring circular symmetry. Increasing model complexity was needed for square, broken square, and rectangular MOSFETs. In these devices, the transistor was broken into two or three separate parts, which give independent contributions to the total drain current and aspect ratio value. A fitting parameter ( α ) was needed to identify the borderline between edge and corner transistors. The model results have been successfully compared with the experimental measurements and the results obtained from numerical simulations.