Alessia Marelli

LDPC Soft Decoding with Reduced Power and Latency in 1X-2X NAND Flash-Based Solid State Drives

The reliability of the non-volatile NAND flash memories, measured in terms of Raw Bit Error Rate (RBER), is reaching critical levels for traditional error detection and correction. Therefore, to ensure data trustworthiness in nowadays NAND flash-based Solid State Drives, it becomes essential exploiting powerful correction algorithms such as the Low Density Parity Check (LDPC). However, the burdens of this approach materialize in an increased NAND flash power consumption due to the increased memory read latencies that translates in limited disk performance. In this work it is performed a comparison between a standard LDPC decoding approach based on hard and soft decisions and an optimized solution called LDPC NAND- Assisted Soft Decision. The simulation results on 2X, 1X and mid-1X MLC NAND flash-based Solid State Drives in terms of NAND flash I/O power consumption, disk read latencies and performance, favor the adoption of the presented solution.

LDPC Soft Decoding with Improved Performance in 1X-2X MLC and TLC NAND Flash-Based Solid State Drives

The reliability of non-volatile NAND flash memories is reaching critical levels for traditional error detection and correction. Therefore, to ensure data trustworthiness in nowadays NAND flash-based Solid State Drives, it is essential to exploit powerful correction algorithms such as the Low Density Parity Check. However, the burdens of this approach materialize in a disk performance reduction. In this work a standard decoding approach is compared with an optimized solution exploiting hardware resources available in NAND flash chips. The simulation results on 2X, 1X and mid-1X MLC and TLC NAND flash-based Solid State Drives in terms of disk bandwidth, average latency, and Quality of Service favor the adoption of the presented solution in different host scenarios and realistic workloads. The proposed solution is particularly effective when high error correction interventions and read- or write-intensive workloads are considered.

Uniform and concentrated read disturb effects in mid-1X TLC NAND flash memories for enterprise solid state drives

The read disturb is one of the most important issues in TLC NAND Flash memories since their usage model is predominantly based on read-intensive applications. The state-of-the-art testing and qualification of the memories against this issue is performed by uniformly stressing the memory blocks with same amount of reads. However, by analyzing several workloads, it appears that the read operations are mostly concentrated in specific page regions. In this work, we characterize the different behavior of a mid-1X TLC NAND Flash under uniform and concentrated read disturb. The results are used to speculate the implications of the workload usage model on the reliability of enterprise Solid State Drives using different error correction strategies and data management policies.

Modeling the Endurance Reliability of Intradisk RAID Solutions for Mid-1X TLC NAND Flash Solid-State Drives

Ensuring data protection in solid state drives (SSDs) is vital in enterprise application scenario. However, as the reliability of their storage medium, namely, the NAND Flash, is decreasing at the same pace of the technology scaling, this activity is becoming nontrivial. The evaluation of different recovery strategies that employ complex error-correction codes and second-level error correction is becoming a de facto. In this paper, we model the endurance reliability of an advanced data protection methodology like the intradisk redundant array of independent disks (RAIDs) applied on mid-1X triple level cell NAND Flash-based SSD. The performed investigations include a parametric analysis of the uncorrectable bit-error rate. By developing a dedicated discrete-time Markov-chain model of an SSD, we evidenced that intradisk RAID5 and RAID6 allow achieving an inherent reliability level compliant with the qualification target for enterprise SSD. Finally, we provide a global picture of the disk economy when intradisk RAID is implemented.

BCH and LDPC Error Correction Codes for NAND Flash Memories

Because NAND devices can’t be manufactured without defects, the use of Error Correction Codes (ECCs) has always been a common practice. While BCH (Bose-Chaudhuri-Hocquenghem) is a de facto standard for consumer applications, LDPC (Low-Density-Parity-Check) codes are a typical choice in the enterprise world. This is especially true when looking at planar (2D) ultra-scaled (e.g. 15nm) NAND. Generally speaking, LDPC offers higher correction capabilities, but BCH remains a good solution when bandwidth requirements are very stringent. This chapter provides an overview of both BCH and LDPC state-of-the-art solutions.

BCH Codes for Solid-State-Drives

Given that the NAND Flash memory is not a very reliable medium, it follows that a Solid State Disk needs some help to achieve a reliability suitable for computing applications: the Error Correction Code (ECC). As the NAND technology scales down, ECC becomes a critical design topic. This chapter deals with BCH, the most common ECC in solid state disks. Two main issues arise when an ECC is used inside an SSD. First of all, the ECC should not limit the bandwidth, being the bottleneck of the entire drive: this translates in a hardware implementation that needs to handle multiple devices (channel) in parallel. At the same time, ECC must avoid erroneous corrections when the error correction capability of the code is overcome, i.e. it must have a high detection property. In this chapter the ECC definitions are reviewed, then the BCH code is presented along with the multi-channel topic. Finally, BCH and LDPC detection property are discussed.

Characterization of TLC 3D-NAND Flash Endurance through Machine Learning for LDPC Code Rate Optimization

The advent of the 3D-NAND Flash memories introduced significant issues in terms of characterization and system-level optimization that can be performed to increase the memory reliability over its lifetime. Indeed, the knobs that a system designer can leverage to this extent are many. In this work we show that the application of machine learning algorithms like data clustering on a large characterization data set of TLC 3D-NAND Flash devices can help the designers in optimizing the countermeasures for improving the memory reliability while reducing their implementation cost.

Design Trade-Offs for NAND Flash-Based SSDs

During the design phase of an SSD, the target application must be always taken into account. In fact, depending on the most important requirements, such as bandwidth, latency or reliability, architecture and cost of the drive might be totally different. Therefore, at the beginning of the development process, a thorough design space exploration is strongly recommended. In this chapter we describe the main actors of the drive architecture and we show how a dedicated CAD tool such as SSDExplorer can be used to optimize the SSD design, given a set of constraints. In particular, we consider 3 different cases: design for maximum bandwidth, design for minimum latency, and performance/reliability trade-off. Of course, in all cases SSD simulations are used to identify the right architecture to achieve the design target, while minimizing the resource request (e.g. number of Flash channels, number of NAND Flash memories, number of processor cores, etc...). For each case, this chapter includes design examples and corresponding simulation results.