Cristian Zambelli

Impact of Intercell and Intracell Variability on Forming and Switching Parameters in RRAM Arrays

The intercell variability of the initial state and the impact of dc and pulse forming on intercell variability as well as on intracell variability in TiN/HfO2/Ti/TiN 1 transistor - 1 resistor (1T-1R) devices in 4-kb memory arrays were investigated. Nearly 78% of devices on particular arrays were dc formed with a wordline (WL) voltage VWL = 1.4 V and a bitline (BL) voltage VBL = 2.3 V, whereas 22% of devices were not formed due to the combined effect of the extrinsic process-induced intercell variability of the initial state and the intrinsic intercell variability after dc forming. Furthermore, pulse-induced forming with pulsewidths on the order of 10 μs (VWL = 1.4 V and VBL = 3.5 V) caused for 86% of devices a low-resistance state. Using a retry algorithm, we achieve 100% of formed devices. To assess and confirm the nature of the variability during forming operation and during cycling, the quantum point-contact model was considered. The modeling results demonstrate a relationship between the forming and the device performance. The cells requiring high energy for the forming operation, due to impurities in the HfO2 deposition during array processing, are those subject to poor switching performance, larger variability, and faster wear out. Devices formed by a pulse-retry algorithm show: 1) shorter endurance and 2) higher variability during cycling.

Nonvolatile memories: Present and future challenges

Due to the rapid development of hand-held electronic devices, the need for high density, low power, high performance SoCs has pushed the well-established embedded memory technologies to their limits. To overcome the existing memory issues, emerging memory technologies are being developed and implemented. The focus is placed on non-volatile technologies, which should meet the high demands of tomorrow applications. The nonvolatile memory technologies being intensively researched today are the Flash memories and the emerging resistive and magnetic type random access memories. This paper presents an overview of device level operation of these nonvolatile memories, with special emphasis on the fabrication-and aging-induced reliability issues.

A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories

In spite of the mature cell structure, the memory controller architecture of Multi-level cell (MLC) NAND Flash memories is evolving fast in an attempt to improve the uncorrected/miscorrected bit error rate (UBER) and to provide a more flexible usage model where the performance-reliability trade-off point can be adjusted at runtime. However, optimization techniques in the memory controller architecture cannot avoid a strict trade-off between UBER and read throughput. In this paper, we show that co-optimizing ECC architecture configuration in the memory controller with program algorithm selection at the technology layer, a more flexible memory sub-system arises, which is capable of unprecedented trade-offs points between performance and reliability.

Statistical analysis of resistive switching characteristics in ReRAM test arrays

The design and the manufacturing of ReRAM test structures allow deeper insight in the performance of the FORMING, RESET, and SET operations at array level, providing details on the process induced variability of the technology, and on the potential sources of failures. Test structures allow also demonstrating the integration capability of the ReRAM technology using a CMOS-compatible process ramping up such non-volatile memory to a maturity level.

Reliability and performance characterization of a mems-based non-volatile switch

In this paper we report data on the reliability and performance characterization of a CMOS-based non-volatile memory (NVM) array, the operating principle of which is based on stiction forces within a MEMS switch. Unlike any other NVM technology, the data retention of this technology improves with increasing temperatures. The switches have been proven to operate over an extremely wide temperature range from −150°C to 300°C, in a 4MRad/s radiation environment and can withstand acceleration forces up to 20,000g. The technology is an ideal candidate for highly reliable non-volatile memory in harsh environmental applications, like auto-motive, defense, space, down-well and geo-thermal. This NVM switch and a tunable RF-MEMS capacitor will be the first products based on this CMOS integrated MEMS platform.

Analysis of reliability/performance trade-off in Solid State Drives

Flash-based Solid-State Drives (SSDs) are rapidly becoming the mainstream solution in the storage panorama thanks to their ruggedness, high performance and reliability. To guarantee the demanding reliability requirements, it is mandatory to embed complex Error Correction Codes (ECCs) and advanced read algorithms. These countermeasures induce an overall performance degradation and hence a non trivial reliability-performance trade-off arises. This work explores such trade-off in a qualitative manner.

LDPC Soft Decoding with Reduced Power and Latency in 1X-2X NAND Flash-Based Solid State Drives

The reliability of the non-volatile NAND flash memories, measured in terms of Raw Bit Error Rate (RBER), is reaching critical levels for traditional error detection and correction. Therefore, to ensure data trustworthiness in nowadays NAND flash-based Solid State Drives, it becomes essential exploiting powerful correction algorithms such as the Low Density Parity Check (LDPC). However, the burdens of this approach materialize in an increased NAND flash power consumption due to the increased memory read latencies that translates in limited disk performance. In this work it is performed a comparison between a standard LDPC decoding approach based on hard and soft decisions and an optimized solution called LDPC NAND- Assisted Soft Decision. The simulation results on 2X, 1X and mid-1X MLC NAND flash-based Solid State Drives in terms of NAND flash I/O power consumption, disk read latencies and performance, favor the adoption of the presented solution.

Electrical characterization of read window in reram arrays under different SET/RESET cycling conditions

In this work a SET/RESET investigation in cycling on ReRAM arrays has been performed, in order to find the most reliable SET/RESET operation conditions. The analysis will compare DC and pulsed SET/RESET operations featuring different durations and voltages on previously DC formed 1T-lR4kbits memory arrays. A thorough analysis of the ReRAM reliability joining the cell-to-cell variability analysis to that of cycling evaluations in complete arrays is addressed. A comparison between DC and Pulse SET/RESET in terms of switching yield, read window, device-to-device uniformity and bit error rate is reported. Finally, the impact of a temperature bake at 1250C on a cycled array is shown to study the temperature impact on the array variability.

A statistical model of erratic erase based on an automated random telegraph signal characterization technique

We propose a new statistical model of the erratic erase based on a new RTS analysis technique. The experimental analysis revealed new interesting features of the erratic erase phenomenon. The overall erased threshold voltage distribution, including tail bits, can be modeled by taking into account the erratic erase behavior whose characteristics can easily be measured by common cycling experiments. The statistical model of the erased threshold voltage obtained in this way can then be used to perform statistical simulation of the bitline leakage current, thus providing a powerful tool in memory design and optimization.

SSDExplorer: A Virtual Platform for Performance/Reliability-Oriented Fine-Grained Design Space Exploration of Solid State Drives

Currently available electronic design automation tools for design space exploration of solid state drives (SSDs) are not able to assess: 1) the device architecture inefficiencies; 2) architecture overdesign for a target performance; and 3) performance degradation caused by the disk usage. These tools feature either an overly high abstraction modeling strategy or lack the required flexibility to perform design exploration. To overcome these problems, this paper proposes SSDExplorer, a tool for fine-grained yet reasonably fast design space exploration of different SSD architectures highlighting possible bottlenecks. To prove its accuracy SSDExplorer has been validated with two real SSDs. SSDExplorer efficiency has been assessed by evaluating the impact of the NAND flash read retry algorithm impact on the SSD performance as a function of its internal architecture.