Piero Olivo

Flash memory cells-an overview

The aim of this paper is to give a thorough overview of flash memory cells. Basic operations and charge-injection mechanisms that are most commonly used in actual flash memory cells are reviewed to provide an understanding of the underlying physics and principles in order to appreciate the large number of device structures, processing technologies, and circuit designs presented in the literature. New cell structures and architectural solutions have been surveyed to highlight the evolution of the flash memory technology, oriented to both reducing cell size and upgrading product functions. The subject is of extreme interest: new concepts involving new materials, structures, principles, or applications are being continuously introduced. The worldwide semiconductor memory market seems ready to accept many new applications in fields that are not specific to traditional nonvolatile memories.

Estimate of signal probability in combinational logic networks

Two methods for the calculation of node signal probabilities in combinational networks are presented. These techniques provide a better accuracy than existing algorithms and a deeper insight in the effects of first-order correlations due to multiple fan-out reconvergences. The proposed algorithms are shown to compare favorably with existing procedures in the analysis of significant benchmarks, both in accuracy and in computational efficiency.<<ETX>>

Quantum-mechanical modeling of accumulation layers in MOS structure

An original method is used for the quantum-mechanical modeling of n-type silicon accumulation layers. Unlike previous methods, which were only valid near 4.2 K, the approach is valid up to room temperature and beyond. The self-consistent results obtained are compared with those of the standard classical model for the accumulation layer, and the differences between them are found to be relevant for the modeling of important device applications. The dependences of the accumulation voltage drop and effective F-N (Fowler-Nordheim) barrier height on oxide electric field and substrate dopine are reported. Experimental F-N current-voltage characteristics of production-quality MOS capacitors are used to validate the quantum results and to show that the standard classical model is not adequate even if the barrier height is considered as a fitting parameter. Approximate analytical expressions giving the semiconductor voltage drop and the effective F-N barrier height as a function of oxide field and substrate doping are derived for and n-type silicon at 77 and 300 K. >

Low‐frequency noise in silicon‐gate metal‐oxide‐silicon capacitors before oxide breakdown

Measurements of the fluctuations in the tunneling current It through a thin SiO2 insulating layer, by means of an ultralow noise measurement set, showed that after a first time interval in which its power spectral density is stationary and proportional to I2t, an on‐off modulation of It arises, just before oxide breakdown. This bistable noise seems to be related to localized phenomena controlled by trapping‐detrapping processes within the oxide. Two possible mechanisms which could give rise to this bistable noise are discussed.

Self-consistent solution of the Poisson and Schrödinger equations in accumulated semiconductor-insulator interfaces

A general method for the study of quantum effects in accumulation layers is presented. The Schrodinger and Poisson equations are self‐consistently solved in a finite quantum box which includes the whole metal‐insulator‐semiconductor structure. An appropriate choice of the boundary conditions allows the achievement of box‐independent results. For the first time, the electrostatical potential and quantum energy levels of an accumulated n‐type semiconductor are fully self‐consistently calculated without considering the electric‐quantum limit approximation. Hence, being able to treat the problem even at room temperature, we report results in the whole range from liquid‐helium temperature to room temperature and beyond. This has been possible because our method allows the calculation of both bound and mobile electron states and their introduction into the Poisson equation on equal footing. The effect of the penetration of the wave functions into the oxide has been determined, and it has been demonstrated that ...

Electron trapping/detrapping within thin SiO2 films in the high field tunneling regime

The work presents the essential features of a model for the electrical behavior of thin SiO2 films in the high field tunneling regime. In particular the carrier trapping/detrapping phenomena, taking place within the insulator and responsible for the current time dependence at constant applied voltages, are considered: the suggestion is proposed that all the oxide Si–O bonds take active part in such processes and explanations are consequently derived for some aspects of previous works not yet convincingly interpreted. The results of a computer program implementing the model are also presented and shown to be in satisfactory agreement with experimental curves which can be fit with a single variable parameter.

Aliasing in signature analysis testing with multiple input shift registers

An investigation of the properties of multiple input shift registers for signature analysis is presented. The assumption of independent errors at the register inputs has been used to model the register behavior as a Markov process whose equations have been solved to obtain the exact dependence of aliasing probabilities as a function of test length, input error probabilities, and feedback structure. Some unique featured of maximum-length registers are proven. Accurate simplified expressions of aliasing probability are derived for use as tools in the evaluation of the coverage. >

Novel design for testability schemes for CMOS ICs

The authors present ideas for addressing the problem of detecting non-stuck-at faults in CMOS circuits that cannot be revealed by means of conventional methods (i.e., as logical errors in the steady-state response). Two techniques are proposed for detecting analog faults, particularly those resulting in intermediate voltages along circuit branches due to faulty conductive paths between the power supply and ground. Involving the conversion of analog faults into stuck-ats and the use of distributed testing logic, these techniques are shown to avoid the drawbacks of previous solutions. A method is proposed for online detection of delay faults, so far not yet considered in the context of design-for-testability. All the proposed techniques require little extra hardware and lead to minimal performance degradations. >

An analytical model for the aliasing probability in signature analysis testing

The Markov chain model of linear feedback shift-registers (LFSRs) for signature analysis testing is analytically solved to obtain the exact expression of the aliasing error probability as a function of test length, error probability, and the structure of the feedback network. The dependence on feedback configuration is explored in depth, and it is proven that maximum-length LFSRs have the best performances with respect to aliasing, regardless of the particular structure of their feedback network. Simplified expressions of aliasing probability are also derived for use as practical tools to design LFSRs for IC signature analysis testing, and a heuristic criterion is given for the identification of peaks in aliasing probability. >

High‐field‐induced voltage‐dependent oxide charge

In this work, we investigate the effects of nondisruptive high‐field stress on the tunneling characteristics of thin SiO2 films (<100 A) and show that after the stress the charge trapped within the oxide reversibly depends on the applied voltage. This is explained with a model where electrons tunnel in and out of trap states located near the injecting interface. Consequently, the trap occupation, hence oxide charge, is determined by transmission coefficients that strongly depend on the actual oxide potential.