Alex Goryachev

Panel: Future SoC verification methodology: UVM evolution or revolution?

With increasing design complexity System on Chip (SoC) verification is becoming a more and more important and challenging aspect of the overall development process. The Universal Verification Methodology (UVM) is thereby a common solution to this problem; although it still keeps some problems unsolved. In this panel leading experts from industry (both users and vendors) and academy will discuss the future of SoC verification methodology.

Verification of Non-Mainline Functions in Todays Processor Chips

In a modern chip development cycle non-mainline / non-functional verification is gaining importance compared to traditional functional verification tasks and takes up to one third of the total verification effort. The purpose of non-mainline logic is to operate, maintain, and debug the chip. Ever-increasing complexity of the chip, thus, directly affects the complexity of the non-mainline logic and as a result, the verification thereof. Moreover, the non-mainline world is no longer pure hardware, but an intricate mix of software and hardware. We claim that traditional constrained-random verification methods are not valid for the non-mainline domain and the verification should be based on usage scenarios. Moreover, these scenarios must be formally specified to avoid ambiguity and allow collaboration of different teams involved in the chip development.

Facing the challenge of new design features: an effective verification approach

Verifying new hardware systems is a daunting task. To reduce the amount of effort involved, verification teams attempt to reuse as much verification IP as possible. We introduce a novel approach for test generation that enables the reuse of verification IP to verify new functionality. This method applies to a significant category of features, which are variations on the functionality of an existing design. Our method is being successfully used in the verification of high-end IBM servers: System p and System z. We compared our technique to alternative approaches and show that it achieves the best quality while reducing manual effort.

Using a High-Level Test Generation Expert System for Testing In-Car Networks

The rising size and complexity of in-car networks call for more advanced and scalable verification solutions. We propose a verification methodology for in-car networks based on a system level test generator tool used for creating massive random biased stimuli, and on coverage and checking monitors. The test generator is an expert system based on an ontology of testing knowledge. A significant challenge is the continuous nature of the stimuli needed to represent the physical environment and the state of the internal components controlled by the vehicles electronic systems. We report on applying our methodology to an example in-car network simulator.

A new test-generation methodology for system-level verification of production processes

The continuing growth in the complexity of production processes is driven mainly by the integration of smart and cheap devices, such as sensors and custom hardware or software components. This naturally leads to higher complexity in fault detection and management, and, therefore to a higher demand for sophisticated quality control tools. A production process is commonly modeled prior to its physical construction to enable early testing. Many simulation platforms were developed to assess the widely varying aspects of the production process, including physical behavior, hardware-software functionality, and performance. However, the efficacy of simulation for the verification of modeled processes is still largely limited by manual operation and observation. We propose a massive random-biased, ontology-based, test-generation methodology for system-level verification of production processes. The methodology has been successfully applied for simulation-based processor hardware verification and proved to be a cost-effective solution. We show that it can be similarly beneficial in the verification of production processes and control.

SLAM: SLice And Merge - Effective Test Generation for Large Systems

As hardware systems continue to grow exponentially, existing functional verification methods are lagging behind, consuming a growing amount of manual effort and simulation time. In response to this inefficiency gap, we developed SLAM, a novel method for test case generation for large systems. Our verification solution combines several scenarios to run in parallel, while preserving each one intact. This is done by automatically and randomly slicing the system model into sub-systems termed slices, and assigning a different scenario to each slice. SLAM increases simulation efficiency by exercising the different system components simultaneously in varied scenarios. It reduces manual effort of test preparation by allowing reuse and mix of test scenarios. We show how to integrate SLAM into the verification cycle to save simulation time and increase coverage. We present real-life results from the use of our solution in the verification process of the latest IBM System p server.

Special session on security verification

Alongside functionality, performance, and power, security is a critical aspect of any system. All software or hardware systems, web applications, and engineered systems built today must comply with stringent requirements in each of these aspects. Security requirements might include that a server must withstand malicious attacks such as stealing or damaging the data or even denial of service. Each of these attacks can have disastrous effects. During the last year alone we saw several examples of such attacks in the media, including: stealing money from bank accounts and ATM machines, bringing down websites, and even breaking into a car computer system while it is driving. In this session we address the challenges of verifying and validating that a system being built fulfills its security requirements. This year is the centennial year for Alan Turing. There are many events taking place throughout the world to celebrate Turings life and his scientific impact. HVC, and this session in particular, is part of these world-wide events. During his relatively brief life, Turing had an enormous impact on many different fields within computer science: theory of computability, artificial intelligence, and of course cryptography and security. During World War II, Turing worked at the British codebreaking center at Bletchley Park. He stood at the head of the section responsible for decoding German naval ciphers. He also invented several methods for breaking codes, with the most famous associated with deciphering the Enigma machine. We devote this session to honoring Alan Turings leadership in breaking German ciphers during WorldWar II and his contribution to cryptography in general. We would like to thank several people who made this session possible: Hana Chockler, Ronny Morad, and Amir Nahir.