Gil Shurek

Constraint-based random stimuli generation for hardware verification

We report on random stimuli generation for hardware verification at IBM as a major applica-tion of various artificial intelligence technologies, including knowledge representation, expert systems, and constraint satisfaction. For more than a decade we have developed several related tools, with huge payoffs. Research and development around this application are still thriving, as we continue to cope with the ever-increasing complexity of modern hardware systems and demanding business environments.

A unified methodology for pre-silicon verification and post-silicon validation

The growing importance of post-silicon validation in ensuring functional correctness of high-end designs increases the need for synergy between the pre-silicon verification and post-silicon validation. We propose a unified functional verification methodology for the pre- and post-silicon domains. This methodology is based on a common verification plan and similar languages for test-templates and coverage models. Implementation of the methodology requires a user-directable stimuli generation tool for the post-silicon domain. We analyze the requirements for such a tool and the differences between it and its pre-silicon counterpart. Based on these requirements, we implemented a tool called Threadmill and used it in the verification of the IBM POWER7 processor chip with encouraging results.

Threadmill: a post-silicon exerciser for multi-threaded processors

Post-silicon validation poses unique challenges that bring-up tools must face, such as the lack of observability into the design, the typical instability of silicon bring-up platforms and the absence of supporting software (like an OS or debuggers). These challenges and the need to reach an optimal utilization of the expensive but very fast silicon platforms lead to unique design considerations - like the need to keep the tool simple and to perform most of its operation on platform without interaction with the environment. In this paper we describe a variety of novel techniques optimized for the unique characteristics of the silicon platform. These techniques are implemented in Threadmill - a bare-metal exerciser targeting multi-threaded processors. Threadmill was used in the verification of the POWER7 processor with encouraging results

Constraint satisfaction for test program generation

A central problem in automatic test generation is solving constraints for memory access generation. A framework, and an algorithm that has been implemented in the Model-Based Test-Generator are described. This generic algorithm allows flexibility in modeling new addressing modes with which memory accesses are generated. The algorithm currently handles address constraint satisfaction for complex addressing modes in the PowerPC, x86, and other architectures.<<ETX>>

Generating concurrent test-programs with collisions for multi-processor verification

We discuss collisions that are of interest to multiprocessor verification. Collisions occur when different processes access a shared resource. We investigate how the results of such collisions can be presented in test programs and suggest implementations for automatically generating such tests and predicting the results of collision scenarios. Most of the ideas presented are the result of years of experience with two multi-processor test generators from IBM (Genie and Genesys-Pro) which are also briefly presented.

Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor

The growing importance of post-silicon validation in ensuring functional correctness of high-end designs has increased the need for synergy between the pre-silicon verification and post-silicon validation. This synergy starts with a common verification plan. It continues with common verification goals and shared tools and techniques. This paper describes our experience in improving this synergy in the pre- and post-silicon verification of IBMs POWER7 processor chip and by leveraging pre-silicon methodologies and techniques in the post-silicon validation of the chip.

The Verification Cockpit – Creating the Dream Playground for Data Analytics over the Verification Process

The Verification Cockpit (VC) is a consolidated platform for planning, tracking, analysis, and optimization of large scale verification projects. Its prime role is to provide decision support from planning to on-going operations of the verification process. The heart of the VC is a holistic centralized data model for the arsenal of verification tools used in modern verification processes. This enables connection of the verification tools and provides rich reporting capabilities as well as hooks to advanced data analytics engines. This paper describes the concept of the Verification Cockpit, its architecture, and implementation. We also include examples of its use in the verification of a high-end processor, while highlighting the capabilities of the platform and the benefits of its use.

A new test-generation methodology for system-level verification of production processes

The continuing growth in the complexity of production processes is driven mainly by the integration of smart and cheap devices, such as sensors and custom hardware or software components. This naturally leads to higher complexity in fault detection and management, and, therefore to a higher demand for sophisticated quality control tools. A production process is commonly modeled prior to its physical construction to enable early testing. Many simulation platforms were developed to assess the widely varying aspects of the production process, including physical behavior, hardware-software functionality, and performance. However, the efficacy of simulation for the verification of modeled processes is still largely limited by manual operation and observation. We propose a massive random-biased, ontology-based, test-generation methodology for system-level verification of production processes. The methodology has been successfully applied for simulation-based processor hardware verification and proved to be a cost-effective solution. We show that it can be similarly beneficial in the verification of production processes and control.

COOL: A Model-Driven and Automated System for Guided and Verifiable Cloud Solution Design

In this paper, we present COOL (ClOud sOlution design tooL), which is a model-driven cloud solution design tool for automatic solution generation, and solution verification. It offers a guided solutioning and customization method starting from complex client business and IT requirements, and enables verification of solution correctness by leveraging constraint satisfaction solvers.

Designer-level verification: an industrial experience story

Designer-level verification (DLV) is now widely accepted as a necessary practice in the hardware industry. More than ever, logic designers are held responsible for the initial validation of modules they develop, before these are released to systematic verification. DLV requires specific tools and methods adapted for designers, who are not full-time verification experts. We present user experience stories and usage statistics, describing how DLV has been practiced in our company, using a dedicated tool developed for this purpose. A typical pattern that emerges is of designers devoting short, fragmented time periods to DLV work, interleaved with other logic development tasks. We observe that the deployed DLV tool supports this mode of work, since it is simple and intuitive. This demonstrates that a suitable tool can help DLV become an integral part of a logic design project.