Alex K. Y. Wong

A near-infrared heart rate measurement IC with very low cutoff frequency using current steering technique

A near-infrared heart-rate measurement IC that processes the photoplethysmographic signal was designed using a 0.35-/spl mu/m CMOS technology. The IC consists of a current-to-voltage (I-V) converter, a buffer, a sample-and-hold circuit, a second-order continuous-time low-pass filter (CT-LPF), a comparator, and a timing circuit that is used to pulse the external light-emitting diode with a very low duty cycle to reduce its power consumption. The current steering technique is employed in the design of the CT-LPF to meet the requirement for very low cutoff frequency. The circuit operates from a 3-V lithium battery, occupies a core area of 0.46 mm/sup 2/ and has a power consumption of 4.5 mW. The measurement results corroborate with simulation results and show that the CT-LPF can achieve a cutoff frequency of as low as 0.25 Hz. This demonstrates the feasibility of current steering technique in the design of filter for low-frequency application.

A Low-Power CMOS Front-End for Photoplethysmographic Signal Acquisition With Robust DC Photocurrent Rejection

A micro-power CMOS front-end, consisting of a transimpedance amplifier (TIA) and an ultralow cutoff frequency lowpass filter for the acquisition of photoplethysmographic signal (PPG) is presented. Robust DC photocurrent rejection for the pulsed signal source is achieved through a sample-and-hold stage in the feed-forward signal path and an error amplifier in the feedback path. Ultra-low cutoff frequency of the filter is achieved with a proposed technique that incorporates a pair of current-steering transistors that increases the effective filter capacitance. The design was realized in a 0.35-mum CMOS technology. It consumes 600 muW at 2.5 V, rejects DC photocurrent ranged from 100 nA to 53.6 muA, and achieves lower-band and upper-band - 3-dB cutoff frequencies of 0.46 and 2.8 Hz, respectively.

An ECG measurement IC using driven-right-leg circuit

In this paper, an electrocardiographic (ECG) signal processing IC, which is used for portable biomedical application, was designed using continuous-time technique. The circuit consists of an instrumentation amplifier (INA) with driven-right-leg circuit (DRL), a 5th order Gm -C low pass filter (Gm-C LPF) operating in sub-threshold mode, and amplifiers. DRL circuit is used to detect small amplitude signal in the presence of large common-mode voltage from the human body. The CMRR of the INA is 78 dB and the Gm-C LPF has a cutoff frequency of 18 Hz. As a result of using the DRL, a small signal can be detected in the presence of large common-mode differential. The circuit consumes 1.23 mW when operating from with a supply voltage of plusmn1.5-V and occupies a core area of 0.94 mm2. The circuit was designed in a 0.35mum CMOS process and simulation results have successfully demonstrated the functionalities

A low power CMOS front-end for photoplethysmongraphic signal acquisition with robust DC Photocurrent Rejection

A micro-power CMOS front-end for photoplethysmographic signal (PPG) acquisition is presented. The circuit is composed of a transimpedance amplifier (TIA), post amplifier and low-pass filter. The TIA is configured with a sample-and-hold (S/H), an error amplifier and a current-sink transistor in feedback to reject DC photocurrent generated from photodiode, which varies from person to person. To reduce power consumption, the LED is pulsed and thus the input to the TIA is a modulated current pulse. The low-pass filter is implemented by using the current-steering technique (CST). The proposed circuit is designed to generate PPG waveform with a fixed DC output to prevent signal saturation by rejecting the input pulsating DC photocurrent from modulated signal. Experimental results show that the circuit works properly from a 2.5-V power supply with a bandpass frequency from 0.1 Hz to 6.5 Hz and has a rejection range from 0.1 muA to 53.6 muA.

A Charge Recycling SAR ADC With a LSB-Down Switching Scheme

This paper presents a new energy efficient successive approximation analog-to-digital converter (ADC) using a charge recycling and LSB-down switching scheme for the capacitive digital-to-analog converter (CDAC). Compared to the conventional binary weighed CDAC, the proposed technique exhibits a 95% reduction in switching energy, a 50% reduction in capacitor area, and with 30% reduction in nonlinearity under the same unit capacitor size and matching condition. The improvement on the switching energy consumption is the best among reported CDAC switching techniques. To validate the technique, a prototype of 10-bit ADC is fabricated in a 0.13 μm CMOS technology using standard capacitors. With a unit capacitor size of 30 fF, the ADC consumes 15.6 μW from a 0.5 V digital supply and a 1 V analog supply. The measured signal-to-noise-plus- distortion ratio is 54.6 dB (ENOB=8.8) at 1.1 MS/s. The FOM is 31.8 fJ/conv.-step, which is among the best when normalized to the same unit capacitor size.

A 0.5-Hz High-Pass Cutoff Dual-Loop Transimpedance Amplifier for Wearable NIR Sensing Device

This brief describes a fully integrated dual-loop transimpedance amplifier with bandpass response for wearable near-infrared (NIR) sensing operating at low frequency: one loop to lower the lower band cutoff frequency and another loop for self-regulating DC photocurrent to prevent saturation at later stages. The circuit was implemented in a 0.35-μm CMOS process and achieved a DC photocurrent rejection ranging from 2.7 to 15 μA and a -3-dB high-pass cutoff frequency from 0.5 to 110 Hz by using on-chip capacitors. Both total harmonic distortion and spurious-free dynamic range are better than -42 dB. It achieves an improvement of 390 times in capacitor reduction compared with the traditional DC rejection technique.

A near-infrared heart rate sensor IC with very low cutoff frequency using current steering technique

In this paper, a near-infrared (NIR) heart-rate sensor IC, which will be used for portable biomedical application, was designed. This sensor consists of a current-to-voltage (I-V) converter, sample-and-hold (S/H) circuit, continuous time low-pass filter (CT-LPF), comparator and clock generation circuitry. Both switched-capacitor and current steering technique are used. The current steering technique is employed in the design of the CT-LPF due to the very low cutoff frequency requirement. As a result, only 20pF and 38pF capacitors are used to implement a 2/sup nd/ order filter with cutoff frequency of 18Hz. The circuit consumes 4.2mW when operating from a 3-V battery and occupies a core area of 0.46mm/sup 2/. The design was fabricated using 0.35/spl mu/m CMOS technology and simulation results show that the circuit works properly.

A High-Linearity Capacitance-to-Digital Converter Suppressing Charge Errors From Bottom-Plate Switches

A high-precision capacitance-to-digital converter (CDC) that is configurable to interface with unipolar or push-pull-type capacitive sensors is presented in this paper. In the conventional switched-capacitor CDC, it is well known that clock feedthroughs and charge injections from top-plate switches can be eliminated by a bottom-plate sampling scheme. However, those charge errors from the bottom-plate switches depend on the digital output and the varying value of the sensing capacitor itself. They will thus affect the overall CDC linearity. When the varying range of the sensing capacitor is wide, the nonlinearity becomes more pronounced. This paper proposes new switching and calibration schemes to reduce these non-idealities. A prototype of a second order CDC employing the proposed techniques in a 0.18 μm CMOS process achieves a 53.2 aF RMS resolution with a 1 ms conversion time. The proposed calibration technique improves the linearity of the CDC from 9.3 bits to 12.3 bits and from 10.1 bits to 13.3 bits in the unipolar and push-pull-type sensing modes, respectively, with a sensing capacitance varying from 0.5 to 3.5 pF. The CDC is also demonstrated with a real-life pressure sensor.

Analysis and Design of a 14-bit SAR ADC using self-calibration DAC

This paper presents the analysis of a calibration technique for high-resolution successive-approximation register analog-to-digital converter (SAR ADC) using a calibration digital-to-analog converter (DAC), which simplifies the complicated relationships among various design parameters and provides design insight that aids in parameter selection. Based on this analysis, an energy-efficient, 14-bit resolution SAR ADC is realized in a 0.18µm CMOS technology. The relationships among the following factors are analyzed in details: (1) the main DAC resolution, (2) the calibration accuracy, (3) the capacitor value to be calibrated, and (4) the parasitic capacitors. Post-layout simulation results are presented and specifically Monte Carlo (MC) shows promising result that is in agreement with the proposed calibration technique.

A NIR CMOS preamplifier with DC photocurrent rejection for pulsed light source

A micro-power transimpedance amplifier is presented to acquire modulated optical signal for heart-rate measurement. The circuit is composed of a transimpedance amplifier (TIA), a sample-and-hold (S/H) circuit, an error amplifier and a current-sink transistor, configured in a feedback loop to reject DC photocurrent generated from photodiode, which varies from person to person. To reduce power consumption, the LED is pulsed and thus the input to the TIA is a modulated current pulse. The proposed circuit is designed to accurately reject the average of the original continuous time signal, rather than that of the pulsed signal. This is achieved by inserting an S/H stage between the TIA and error amplifier. Simulation results show that the circuit works properly from a 2-V power supply and has a rejection range from 40 muA to 95 muA.