Kong-Pang Pun

An efficient MFCC extraction method in speech recognition

This paper introduces a new algorithm of extracting MFCC for speech recognition. The new algorithm reduces the computation power by 53% compared to the conventional algorithm. Simulation results indicate the new algorithm has a recognition accuracy of 92.93%. There is only a 1.5% reduction in recognition accuracy compared to the conventional MFCC extraction algorithm, which has an accuracy of 94.43%. However, the number of logic gates required to implement the new algorithm is about half of the MFCC algorithm, which makes the new algorithm very efficient for hardware implementation

A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC

A 0.5-V third-order one-bit fully-differential continuous-time DeltaSigma modulator is presented. The presented modulator architecture uses true low-voltage design techniques, and does not require internal voltage boosting or low-threshold devices. A return-to-open architecture that enables the ultra-low-voltage realization of return-to-zero signaling for the feedback DAC is proposed. The ultra-low-voltage operation is further enabled by a body-input gate-clocked comparator, and body-input operational transconductance amplifiers for the active-RC loop filter. Fabricated on a 0.18-mum CMOS process, the modulator achieves a peak SNDR of 74 dB in a 25 kHz bandwidth, and occupies an area of 0.6 mm2; the modulator core consumes 300 muW.

Reversed nested Miller compensation with voltage buffer and nulling resistor

This paper presents a new reversed nested Miller compensation technique for multistage operational amplifier (opamp) design. The new compensation technique inverts the sign of the right half complex plane zero and shifts the frequency of the complex conjugate poles to a higher frequency. Simulation results indicate that the gain-bandwidth product and settling time are improved by factors of two and three, respectively, without degrading stability and power consumption. To verify the proposed technique, a three-stage opamp is fabricated with 0.6-/spl mu/m CMOS technology. The measured results of the test circuit agree with the results that are obtained from theoretical analysis and circuit simulation.

A near-infrared heart rate measurement IC with very low cutoff frequency using current steering technique

A near-infrared heart-rate measurement IC that processes the photoplethysmographic signal was designed using a 0.35-/spl mu/m CMOS technology. The IC consists of a current-to-voltage (I-V) converter, a buffer, a sample-and-hold circuit, a second-order continuous-time low-pass filter (CT-LPF), a comparator, and a timing circuit that is used to pulse the external light-emitting diode with a very low duty cycle to reduce its power consumption. The current steering technique is employed in the design of the CT-LPF to meet the requirement for very low cutoff frequency. The circuit operates from a 3-V lithium battery, occupies a core area of 0.46 mm/sup 2/ and has a power consumption of 4.5 mW. The measurement results corroborate with simulation results and show that the CT-LPF can achieve a cutoff frequency of as low as 0.25 Hz. This demonstrates the feasibility of current steering technique in the design of filter for low-frequency application.

A Low-Power CMOS Front-End for Photoplethysmographic Signal Acquisition With Robust DC Photocurrent Rejection

A micro-power CMOS front-end, consisting of a transimpedance amplifier (TIA) and an ultralow cutoff frequency lowpass filter for the acquisition of photoplethysmographic signal (PPG) is presented. Robust DC photocurrent rejection for the pulsed signal source is achieved through a sample-and-hold stage in the feed-forward signal path and an error amplifier in the feedback path. Ultra-low cutoff frequency of the filter is achieved with a proposed technique that incorporates a pair of current-steering transistors that increases the effective filter capacitance. The design was realized in a 0.35-mum CMOS technology. It consumes 600 muW at 2.5 V, rejects DC photocurrent ranged from 100 nA to 53.6 muA, and achieves lower-band and upper-band - 3-dB cutoff frequencies of 0.46 and 2.8 Hz, respectively.

Wideband digital correction of I and Q mismatch in quadrature radio receivers

I/Q mismatches are common in radio receivers, which apply quadrature demodulation schemes. Numerous methods have been developed to estimate and correct these errors for narrow-band signals. In this paper a wideband correction method is introduced. First the frequency-dependent I/Q mismatches are estimated by local test signal injection. Then a digital filter is constructed to correct them. With this method, a significant amount of image rejection over a broad bandwidth can be achieved as demonstrated by high-level simulations.

An ECG measurement IC using driven-right-leg circuit

In this paper, an electrocardiographic (ECG) signal processing IC, which is used for portable biomedical application, was designed using continuous-time technique. The circuit consists of an instrumentation amplifier (INA) with driven-right-leg circuit (DRL), a 5th order Gm -C low pass filter (Gm-C LPF) operating in sub-threshold mode, and amplifiers. DRL circuit is used to detect small amplitude signal in the presence of large common-mode voltage from the human body. The CMRR of the INA is 78 dB and the Gm-C LPF has a cutoff frequency of 18 Hz. As a result of using the DRL, a small signal can be detected in the presence of large common-mode differential. The circuit consumes 1.23 mW when operating from with a supply voltage of plusmn1.5-V and occupies a core area of 0.94 mm2. The circuit was designed in a 0.35mum CMOS process and simulation results have successfully demonstrated the functionalities

An HMM-based speech recognition IC

This paper presents the design, simulation and measurement results of a Hidden Markov Model (HMM) based isolated word recognizer IC with double mixtures. Table look-up technique is employed in this design. The chip operates at 20 MHz at 3.3 V. The recognition time is 0.5 s for a 50-word speech library. The speech IC has been verified with 467 test speech data and the recognition accuracy is 93.8%. A reference software recognizer using the same algorithm and speech library has a recognition accuracy of 94.2%. The new speech IC that uses a table look up to reduce the complexity of the circuit has approximately the same recognition accuracy as an ideal software recognizer.

A Fully Differential Band-Selective Low-Noise Amplifier for MB-OFDM UWB Receivers

A band-selective low-noise amplifier (BS-LNA) for multiband orthogonal frequency-division multiplexing ultra-wide-band (UWB) receivers is presented. A switched capacitive network that controls the resonant frequency of the LC load for the band selection is used. It greatly enhances the gain and noise performance of the LNA in each frequency band without increasing power consumption. Moreover, a fully differential configuration is employed to suppress the common-mode switching noise that is generated during the band transition interval. Fabricated in a 0.18-mum CMOS process, the BS-LNA achieves a peak power gain of 16 dB, a minimum noise figure of 2.74 dB, and an third-order input intercept point of -8.8 dBm at a current consumption of 7.95 mA from a 1.5-V supply. Little performance degradation is observed when the current consumption is reduced by half. The experimental results also show a worst-case band-switching time of less than 3.4 ns, with a peak switching noise voltage of less than 70 muV at the output.

Quadrature sampling schemes with improved image rejection

A fundamental problem of analog quadrature sampling circuits is the in-phase/quadrature-phase (I/Q) mismatch, which adversely affects their image rejection performance. This brief proposes two new quadrature sampling circuits for the sampling of complex intermediate frequency signals with high image rejection performance. The first circuit reduces the I/Q mismatches by time-sharing of the sampling capacitors and by employing a special clocking scheme. The second circuit integrates a first-order complex notch filter to provide extra image rejection. Both circuits are very simple and they introduce little overhead compared with conventional circuits. Circuit simulations show that for 2% channel mismatch, the first circuit removes completely the image interferer, and the second one achieves over 70 dB of image rejection ratio in a narrow band around direct current, while the conventional circuits achieve only about 40 dB.