Alexa Doboli

System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search

This paper presents two heuristics for automatic hardware/software partitioning of system level specifications. Partitioning is performed at the granularity of blocks, loops, subprograms, and processes with the objective of performance optimization with a limited hardware and software cost. We define the metric values for partitioning and develop a cost function that guides partitioning towards the desired objective. We consider minimization of communication cost and improvement of the overall parallelism as essential criteria during partitioning. Two heuristics for hardware/software partitioning, formulated as a graph partitioning problem, are presented: one based on simulated annealing and the other on tabu search. Results of extensive experiments, including real-life examples, show the clear superiority of the tabu search based algorithm.

Scheduling with bus access optimization for distributed embedded systems

In this paper, we concentrate on aspects related to the synthesis of distributed embedded systems consisting of programmable processors and application-specific hardware components. The approach is based on an abstract graph representation that captures, at process level, both dataflow and the flow of control. Our goal is to derive a worst case delay by which the system completes execution, such that this delay is as small as possible; to generate a logically and temporally deterministic schedule; and to optimize parameters of the communication protocol such that this delay is guaranteed. We have further investigated the impact of particular communication infrastructures and protocols on the overall performance and, specially, how the requirements of such an infrastructure have to be considered for process and communication scheduling. Not only do particularities of the underlying architecture have to be considered during scheduling but also the parameters of the communication protocol should be adapted to fit the particular embedded application. The optimization algorithm, which implies both process scheduling and optimization of the parameters related to the communication protocol, generates an efficient bus access scheme as well as the schedule tables for activation of processes and communications.

VHDL system-level specification and partitioning in a hardware/software co-synthesis environment

This paper deals with the problems of system-level specification and partitioning in hardware/software co-design. It first discusses the implication of using VHDL as an implementation-independent specification language. A message passing communication mechanism is proposed to relax the strict synchronization imposed by the simulation-based semantics of VHDL. A partitioning technique is then described which is used to partition the VHDL specification into a hardware part and a software part. The partitioning is carried out during the compilation process of VHDL into a design representation which identifies the hardware/software boundary, while capturing hardware and software in a uniform way to allow efficient co-synthesis of both parts. The VHDL compiler and the partitioning algorithm function as the front end of a hardware/software co-synthesis environment which is built on the design representation.<<ETX>>

Hardware/software partitioning with iterative improvement heuristics

The paper presents two heuristics for hardware/software partitioning of system level specifications. The main objective is to achieve performance optimization with a limited hardware and software cost. We consider minimization of communication cost and improvement of the overall parallelism as essential criteria. One of the heuristics is based on simulated annealing and the other on tabu search. Experiments show the superiority of the tabu search based algorithm.

Hardware/software partitioning of VHDL system specifications

This paper presents an approach far system level specification and hardware/software partitioning with VHDL. The implications of using VHDL as a specification language are discussed and a message passing mechanism is proposed for process interaction. We define the metric values for partitioning and develop a cost function that guides our heuristics towards performance optimization under hardware and software cost constraints. Experimental results are presented.

Timing constraint specification and synthesis in behavioral VHDL

This paper describes two methods to specify timing constraints in behavioral VHDL for high-level synthesis purposes. The first method specifies timing constraints on sequences of statements by using predefined procedures. The second method provides support for specification of timing constraints across process borders based on concurrent assert statements on signal events. The paper discusses also an approach to synthesize hardware with timing constraints and concentrates in particular on how to ensure consistency between the behavior of the simulation model and that of the synthesized hardware.

Process scheduling for performance estimation and synthesis of hardware/software systems

The paper presents an approach to process scheduling for embedded systems. Target architectures consist of several processors and ASICs connected by shared busses. We have developed algorithms for process graph scheduling based on list scheduling and branch and bound strategies. One essential contribution is in the manner in which information on process allocation is used in order to efficiently derive a good quality or optimal schedule. Experiments show the superiority of these algorithms compared to previous approaches like critical path heuristics and ILP based optimal scheduling. An extension of our approach allows the scheduling of conditional process graphs capturing both data and control flow. In this case a schedule table has to be generated so that the worst case delay is minimized.

Post-synthesis back-annotation of timing information in behavioral VHDL

Abstract This paper presents an approach to back-annotation of timing information in behavioral VHDL descriptions. In our approach, a behavioral VHDL description specifies the functionality and timing constraints of a design which is synthesized by a high-level synthesis tool. After synthesis the timing information of the design is back-annotated to the original VHDL description which is then used for simulation. A distinct feature of our approach is that it does not rely on the so called well-timed assumption which requires that the execution of every alternative path should take exactly the same time. This reflects the synthesis strategy adopted by our system, namely different execution times can be synthesized for the alternative paths in a constrained statement sequence, as long as all these times satisfy the user-specified timing requirements. Thus, our back-annotation strategy solves the tracing of the actually executed path through a time-constrained sequence and the dynamic selection of the respective synthesized time for simulation. The elaborated algorithms are illustrated by examples.