Alexander Albicki

Low power design using double edge triggered flip-flops

In this paper we study the power savings possible using double edge triggered (DET), instead of, conventional single edge triggered (SET) flip-flops. We begin the paper by introducing a set of novel D-type double edge triggered flip-flops which can be implemented with fewer transistors than any previous design. The power dissipation in these flip-flops and single edge triggered flip-flops is compared via architectural level studies, analytical considerations and simulations. The analysis includes an implementation independent study on the effect of input sequences in the energy dissipation of single and double edge triggered flip-flops. The system level energy savings possible by using registers consisting of double edge triggered flip-flops, instead of single edge triggered flip-flops, is subsequently explored. The results are extremely encouraging, indicating that double edge triggered flip-flops are capable of significant energy savings, for only a small overhead in complexity. >

Data extraction for effective non-intrusive identification of residential power loads

A completely effective technology for monitoring energy consumption and switching patterns of multiple electrical loads is desired yet not available. While parallel metering of multiple loads is possible, it is rarely cost effective and requires several installations and maintenance checks that disrupt a monitored business or residence. This report describes how non-intrusive monitoring methods for residences have been extended with several novel techniques to identify electrical loads and measure energy consumed by each.

Nonintrusive identification of electrical loads in a three-phase environment based on harmonic content

This paper describes a signature construction for identifying loads based upon harmonic content of the current measured at a metering socket. Data gathered from ten loads at a commercial site served to experimentally validate the signature construction. The repeatability of current harmonics was investigated during transients and steady-states of several single, split-phase, and three-phase loads monitored in isolation.

Algorithm for nonintrusive identification of residential appliances

An algorithm has been developed to use at a central processing site for identifying appliances and appliance usage at remotely monitored residences. This algorithm is part of a nonintrusive system that uses sampled data for real and reactive power accumulated over an extended period of time. Using a logic analysis, the algorithm can recognize at least six major appliances, including a heat pump, as well as any two appliances that turn on or off at nearly the same time. Data from several residences in the Rochester, NY, and Columbus, OH, areas have been analyzed during this study.

Extended hyperbolic congruential frequency hop code: generation and bounds for cross- and auto-ambiguity function

We propose a new frequency hop code, called the extended hyperbolic congruential (EHC) code. The properties of the code, determined via hit array analysis, indicate almost ideal cross- and auto-ambiguity characteristics. Furthermore, the code can be defined recursively, enabling a simple hardware implementation. This makes the code attractive for code division multiple access (CDMA) communication systems.

Low power and high speed multiplication design through mixed number representations

A low power multiplication algorithm and its VLSI architecture using a mixed number representation is proposed. The reduced switching activity and low power dissipation are achieved through the Sign-Magnitude (SM) notation for the multiplicand and through a novel design of the Redundant Binary (RB) adder and Booth decoder. The high speed operation is achieved through the Carry-Propagation-Free (CPF) accumulation of the Partial Products (PP) by using the RB notation. Analysis showed that the switching activity in the PP generation process can be reduced on average by 90%. Compared to the same type of multipliers, the proposed design dissipates much less power and is 18% faster on average.

Reducing power dissipation in CMOS circuits by signal probability based transistor reordering

This paper introduces novel transistor reordering schemes to reduce the expected or average dynamic power dissipation in CMOS circuits. The transistor reordering is based on the signal probability values at the inputs of the gates. The paper begins with a simple analytical model for the dynamic power dissipation in a static NAND gate. The model is used to derive an algorithm for transistor reordering which reduces dynamic power dissipation. A simulation technique for accurately measuring the power dissipation in NAND gates is also presented, along with the results of the reordering algorithm. A transistor reordering algorithm for CMOS complex gates is subsequently presented. Transistor reordering is found to be an effective way to reduce power dissipation in all of these circuits, with the reduction in dynamic power dissipation compared to the worst case configuration, being as high as 50% in some instances. The limited overhead associated with transistor reordering encourage its application as a low power design technique.

Low power via reduced switching activity and its application to PLAs

In this paper a systematic study of the expected switching activity (ESA) in combinational logic circuits is presented. Based on this study, a technique for reducing the power dissipation in two-level combinational logic is presented. The paper also discusses the switching activity in multilevel circuits.<<ETX>>

A pass transistor regular structure for implementing multi-level combinational circuits

Implementation of multi-level combinational circuits using pass transistors and transmission gates is presented. The circuits are built with a new set of pass transistor gates, creating a network with well defined logic values at any node. A method to identify certain logic patterns is presented with the goal to reduce the number of pass transistor gates required to implement a logic function. SPICE simulations verified by the simulation of an example circuit show significant speed improvements for combinational circuits designed with pass transistor gates.<<ETX>>

Design of robust-path-delay-fault-testable combinational circuits by Boolean space expansion

A procedure for the design of robustly path-delay-fault testable two-level circuits by adding extra inputs to the circuits, using the method called Boolean space expansion is proposed. 100% path delay fault testable two-level circuits are achieved with area overhead in the range of 3% to 30%. A procedure to make the multilevel circuits fully testable is also reported. The results for several ISCAS benchmark circuits are presented.<<ETX>>