Andrzej Krasniewski

Circular self-test path: a low-cost BIST technique for VLSI circuits

A technique for designing self-test VLSI circuits, referred to as circular self-test path (CSTP), is introduced. The CSTP is a feedback shift register (output of the last flip-flop is supplied to the first flip-flop) with a data communication capability. It serves simultaneously for test pattern generation and test response compaction, thereby minimizing the test schedule complexity; the whole chip is tested in a single test session. A distinguishing attribute of built-in self-test (BIST) chips designed using this technique is a low silicon area overhead, slightly exceeding that of scan path designs, but substantially lower than that of built-in logic block observer (BILBO)-based circuits. Theoretical and simulation studies were performed to demonstrate that the test pattern generation efficiency of the CTSP is comparable to that of a pseudorandom generator, regardless of the functionality of the circuit under test. >

Application-dependent testing of FPGA delay faults

To ensure correct operation of an FPGA based system with regard to timing characteristics, an application-dependent FPGA testing, i.e. testing of an FPGA programmed to implement a user-defined function, must be performed. We propose a procedure for application-dependent self testing of an in-circuit reprogrammable FPGA and develop BIST schemes that preserve the FPGA timing. For these schemes, the reconfiguration of a portion of the FPGA into test resources has no impact on the timing characteristics of that part of the FPGA which is currently being tested. We also present a method for enhancing the susceptibility of FPGA delay faults to random testing. It is based on modifying the functions of programmable logic components in the section under test. We compare the efficiency of the self-test scheme that uses this method with the earlier reported BIST techniques that rely on the design of test pattern generators best suited for pseudoexhaustive testing of delay faults.

Flexibility and adaptability in engineering education: an academic institution perspective

To survive in the highly competitive environment, an engineering education institution must offer its students an attractive system of study. Essential features of such a system are flexibility and adaptability. Flexibility means that the system provides a large number of diverse opportunities and allows the students to take advantage of the existing diversity. A flexible system of study should provide for multiple entry and exit points, and for several areas of concentration within one or more fields of study. Students freedom in design of his/her individual program of study should not be restricted by an excessive number of compulsory courses. The student should also be allowed to adjust the course load in each term to his/her background and speed of learning. Adaptability of a system of study means that adjustments in curricula, reflecting advances in science and technology, trends on the labor market, and evolution of international standards of engineering education, can easily be performed. In this paper, the authors discuss how to restructure a system of study to make it more flexible and adaptable. The general ideas are illustrated with an example of a recently restructured system of engineering education at their institution-the Faculty of Electronics and Information Technology, Warsaw University of Technology, Poland. They demonstrate that flexibility and adaptability of the system of study contribute to the overall quality of education.

Testing FPGA delay faults in the system environment is very different from "ordinary" delay fault testing

Explains differences between testing delay faults in FPGAs and testing delay faults in circuits whose combinational sections can be represented as gate networks. Formulates - in a form suitable for analysis of LUT-based FPGAs - conditions that allow one to check whether or not a given input pair is a test of specific type (non-robust, robust, etc.). The presented theoretical results are shown to simplify an analysis of the various methods for enhancing the effectiveness of detection of FPGA delay faults.

Concurrent error detection in sequential circuits implemented using FPGAs with embedded memory blocks

We propose a low-overhead concurrent error detection scheme for a sequential circuit implemented using an FPGA with embedded memory blocks (EMBs). The presented scheme is proven to detect each permanent or transient fault associated with a single input or output of any component of the circuit that leads to an incorrect state transition. Such faults are detected with no latency. Our technique requires significantly less extra logic than the earlier proposed schemes for concurrent error detection in sequential circuits. For a large percentage of the examined benchmark circuits, no extra EMBs and just 3 extra LUTs are needed; for other circuits, the number of extra EMBs is quite limited - on average, an overhead in terms of the number of EMBs is 13.6%.

Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPFAs

We present an extension of a procedure for self-testing of an FPGA that implements a user-defined function. This extension, intended to improve the detectability of FPGA delay faults, exploits the reconfigurability of FPGAs and is based on modifying the functions of LUTs in the section under test. A modification procedure replaces a user-defined function of each LUT with a specific function that preserves the blocking capability and input-output transition pattern of the original function. We show that the proposed method significantly increases the susceptibility of FPGA delay faults to random testing.

Concurrent error detection for finite state machines implemented with embedded memory blocks of SRAM-based FPGAs

We propose a cost-efficient concurrent error detection (CED) scheme for finite state machines (FSMs) designed for implementation with embedded memory blocks (EMBs) available in todays SRAM-based FPGAs. The proposed scheme is proven to detect each permanent or transient fault associated with a single input or output of any component of the circuit that results in its incorrect state or output. The experimental results obtained using our proprietary FSM synthesis tool show that despite the heterogeneous structure of the proposed CED scheme, the overhead is very low. For the examined benchmark circuits, the circuitry overhead in terms of extra EMBs is in the range of 6.3-56.3%, with an average value of 27.2%, whereas the combined overhead (EMBs and logic cells) calculated under pessimistic assumptions is in the range of 20.7-63.8%, with an average value of 32.2%. This compares favorably with the earlier proposed solutions applicable to conventional FSM designs based on gates and flip-flops for which an overhead exceeding 100% is quite typical.

Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices

A model of the combinational section of a programmable device suitable for an analysis of testability of delay faults is proposed. All relevant factors that affect the evaluation of testability of path delay faults are identified and their impact on the outcome of the evaluation is discussed. A detailed analysis, supported by quantitative results, focuses on the selection of the set of target faults in terms of a class of logical paths and on the concept of defining testability measures for physical paths rather than for logical paths. Practical guidelines are formulated for the development of a procedure for the evaluation of testability of path delay faults.

Enhancing Detection of Delay Faults in FPGA-Based Circuits by Transformations of LUT Functions

Abstract An application-dependent FPGA testing, i.e. testing of an FPGA configured to implement a user-defined function, must be performed to ensure correct operation of an FPGA-based system with regard to timing characteristics. Assuming application-dependent self-testing, a method for enhancing the susceptibility of FPGA delay faults to random testing has been developed. It is based on modifying the functions of LUT-based programmable logic blocks in the section under test: a user-defined function of each LUT is replaced with a specific function that preserves the input-output transition pattern of the original function and maximizes the output activity ofthe LUT.

Concurrent Error Detection for Combinational Logic Blocks Implemented with Embedded Memory Blocks of FPGAs

A concurrent error detection (CED) scheme for combinational logic blocks implemented with embedded memory blocks (EMBs) available in todays FPGAs is proposed. The scheme guarantees the detection of each permanent or transient fault resulting in a single-bit error at the input or output of any component of the circuit. Extensions of the basic scheme aimed at increasing the set of target faults are also presented. For the examined benchmark circuits, an average overhead associated with the proposed CED scheme is 24.7%, whereas for the earlier presented CED techniques applicable to conventional gate-based designs, an average overhead for the same circuits is in the range of 60%. The proposed technique offers also lower speed degradation and lower extra power consumption than the techniques intended for conventional gate-based designs.