Alexander Badmaev

Wafer-Scale Fabrication of Separated Carbon Nanotube Thin-Film Transistors for Display Applications

Preseparated, semiconductive enriched carbon nanotubes hold great potential for thin-film transistors and display applications due to their high mobility, high percentage of semiconductive nanotubes, and room-temperature processing compatibility. Here in this paper, we report our progress on wafer-scale processing of separated nanotube thin-film transistors (SN-TFTs) for display applications, including key technology components such as wafer-scale assembly of high-density, uniform separated nanotube networks, high-yield fabrication of devices with superior performance, and demonstration of organic light-emitting diode (OLED) switching controlled by a SN-TFT. On the basis of separated nanotubes with 95% semiconductive nanotubes, we have achieved solution-based assembly of separated nanotube thin films on complete 3 in. Si/SiO(2) wafers, and further carried out wafer-scale fabrication to produce transistors with high yield (>98%), small sheet resistance ( approximately 25 kOmega/sq), high current density ( approximately 10 microA/microm), and superior mobility ( approximately 52 cm(2) V(-1) s(-1)). Moreover, on/off ratios of >10(4) are achieved in devices with channel length L > 20 microm. In addition, OLED control circuit has been demonstrated with the SN-TFT, and the modulation in the output light intensity exceeds 10(4). Our approach can be easily scaled to large areas and could serve as critical foundation for future nanotube-based display electronics.

CMOS-Analogous Wafer-Scale Nanotube-on-Insulator Approach for Submicrometer Devices and Integrated Circuits Using Aligned Nanotubes

Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits.

Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections

1D carbon nanotube FET (CNFET)-based circuits offer 4.6times faster FO4 speed and 12times energy-delay product improvement over 32nm node Si CMOS (including diameter and doping variations), provided circuits can be built that are immune to misaligned and metallic nanotubes. A design technique that guarantees correct logic operation in the presence of misaligned nanotubes is also presented.

2,4,6-Trinitrotoluene (TNT) Chemical Sensing Based on Aligned Single-Walled Carbon Nanotubes and ZnO Nanowires

2010 WILEY-VCH Verlag Gmb Chemical sensors based on one-dimensional (1D) nanostructures have attracted a great deal of attention because of their exquisite sensitivity and fast response to the surrounding environment. In addition, both carbon nanotubes and metal oxide nanowires are promising candidates for building an electronic nose (e-nose) system. Among these materials, semiconductor single-walled carbon nanotubes (SWNTs) are molecular-scale wires composed entirely of surface atoms, which should be ideal for the direct electrical detection and are expected to exhibit excellent sensitivity to surrounding chemical and biological species. Kong et al. initially utilized SWNT field-effect transistors (FETs) to detect nitrogen dioxide (NO2) and ammonia (NH3), and demonstrated a detection limit of 2 ppm for NO2 and 0.1% for NH3. [11] Subsequently, such SWNT-based chemical sensors have been applied to detect a wide variety of chemicals and the detection limits have been significantly improved. Qi et al. fabricated large arrays of functionalized SWNTsensors, and the detection limit of NO2 was lowered to 100 ppt. [12] In addition, metal oxide nanowires have been widely studied and demonstrated with great potential for chemical sensing applications. Recently, due to the threat of terrorism and the need for homeland security, significant progress has been achieved in the detection of both explosives and nerve agents, such as 2,4,6-trinitrotoluene (TNT), 2,4-dinitrotoluene (DNT), hexogen (DRX), and dimethyl methylphosphonate (DMMP). One of the leading candidates is 1D nanostructure-based chemoresistors or FETs. Snow et al. and Wang et al. have reported the detection of DMMP at ppb level by using SWNT and SnO2 nanowire-based chemical sensors, respectively. However, to our knowledge, there were only a few reports on the use of 1D nanostructure-based chemoresistors and FETs for detecting explosives, and the detection mechanism is still unclear. In addition, electronic devices fabricated on mechanically flexible substrates have recently attracted enormous attention, due to the proliferation of handheld applications in portable electronics, aerospace science, and civil engineering. Currently, conventional microfabrication techniques or printing methods can be applied to SWNTs on plastic substrates to form devices, allowing inexpensive mass-production and conformable electronics. In this paper, we report the transfer of aligned semiconductor SWNTs onto cloth fabric and successful fabrication of flexible SWNTchemical sensors, which have great potential for wearable electronics. These SWNT chemical sensors exhibited good sensitivity of trace chemical vapors, including 8 ppb TNT and 40 ppb NO2, at room temperature. Besides, to realize the concept of an electronic nose (e-nose) system for explosives, we also fabricated ZnO nanowire-based chemical sensors, which showed a detection limit of 60 ppb for TNT molecules at room temperature. To our knowledge, this is the first TNT sensor built on the basis of metal oxide nanowires. In addition, the detection limit of our chemical sensors is close to the limit of 1.5 ppb TNT set by the U.S. Occupational Safety and Health Administration. The flexible TNT sensors can find immediate applications in systems that demand mechanical flexibility, light weight, and high sensitivity. The fabrication of flexible SWNTchemical sensors started with the synthesis of SWNTs on quartz substrates using a chemical vapor deposition (CVD) method, which have been reported by us and other groups. After growth, we adapted a facile method to transfer the aligned nanotubes from the original substrate to fabric. In brief, a 100-nm-thick gold film was first deposited on the original substrate with aligned SWNTs, followed by applying a thermal tape to peel off the gold film and nanotubes from the growth substrate. The gold film with SWNTs on the thermal tape were pressed against a piece of textile fabric, which was pre-coated with polyethylene at elevated temperature and then transferred from thermal tape onto textile fabric, which had a 50-nm Ti layer as back-gate electrode and 2-mm-thick SU-8 as gate dielectric layer. The thermal tape was released, and KI/I2 gold etchant was then applied to remove gold films. Finally, Ti (0.5 nm) and Pd (40 nm) were deposited on the transferred SWNTs as source/drain electrodes. A schematic diagram of a flexible SWNT chemical sensor is shown in Figure 1a. Figure 1b shows an optical photograph of flexible aligned SWNT FETs on a textile fabric. It can be clearly seen from the SEM image (right) that the nanotubes bridge the two electrodes. Figure 1c displays the current–gate-voltage (I–Vg) characteristics of a typical flexible transistor on fabric before and after electrical breakdown. The device showed significant improvement for the

Radio frequency and linearity performance of transistors using high-purity semiconducting carbon nanotubes.

This paper reports the radio frequency (RF) and linearity performance of transistors using high-purity semiconducting carbon nanotubes. High-density, uniform semiconducting nanotube networks are deposited at wafer scale using our APTES-assisted nanotube deposition technique, and RF transistors with channel lengths down to 500 nm are fabricated. We report on transistors exhibiting a cutoff frequency (f(t)) of 5 GHz and with maximum oscillation frequency (f(max)) of 1.5 GHz. Besides the cutoff frequency, the other important figure of merit for the RF transistors is the device linearity. For the first time, we report carbon nanotube RF transistor linearity metrics up to 1 GHz. Without the use of active probes to provide the high impedance termination, the measurement bandwidth is therefore not limited, and the linearity measurements can be conducted at the frequencies where the transistors are intended to be operating. We conclude that semiconducting nanotube-based transistors are potentially promising building blocks for highly linear RF electronics and circuit applications.

Metal Contact Engineering and Registration-Free Fabrication of Complementary Metal-Oxide Semiconductor Integrated Circuits Using Aligned Carbon Nanotubes

Complementary metal-oxide semiconductor (CMOS) operation is very desirable for logic circuit applications as it offers rail-to-rail swing, larger noise margin, and small static power consumption. However, it remains to be a challenging task for nanotube-based devices. Here in this paper, we report our progress on metal contact engineering for n-type nanotube transistors and CMOS integrated circuits using aligned carbon nanotubes. By using Pd as source/drain contacts for p-type transistors, small work function metal Gd as source/drain contacts for n-type transistors, and evaporated SiO(2) as a passivation layer, we have achieved n-type transistor, PN diode, and integrated CMOS inverter with an air-stable operation. Compared with other nanotube n-doping techniques, such as potassium doping, PEI doping, hydrazine doping, etc., using low work function metal contacts for n-type nanotube devices is not only air stable but also integrated circuit fabrication compatible. Moreover, our aligned nanotube platform for CMOS integrated circuits shows significant advantage over the previously reported individual nanotube platforms with respect to scalability and reproducibility and suggests a practical and realistic approach for nanotube-based CMOS integrated circuit applications.

Self-Aligned Fabrication of Graphene RF Transistors with T-Shaped Gate

Exceptional electronic properties of graphene make it a promising candidate as a material for next generation electronics; however, self-aligned fabrication of graphene transistors has not been fully explored. In this paper, we present a scalable method for fabrication of self-aligned graphene transistors by defining a T-shaped gate on top of graphene, followed by self-aligned source and drain formation by depositing Pd with the T-gate as a shadow mask. This transistor design provides significant advantages such as elimination of misalignment, reduction of access resistance by minimizing ungated graphene, and reduced gate charging resistance. To achieve high-yield scalable fabrication, we have combined the use of large-area graphene synthesis by chemical vapor deposition, wafer-scale transfer, and e-beam lithography to deposit T-shaped top gates. The fabricated transistors with channel lengths in the range of 110-170 nm exhibited excellent performance with peak current density of 1.3 mA/μm and peak transconductance of 0.5 mS/μm, which is one of the highest transconductance values reported. In addition, the T-gate design enabled us to achieve graphene transistors with extrinsic current-gain cutoff frequency of 23 GHz and maximum oscillation frequency of 10 GHz. These results represent important steps toward self-aligned design of graphene transistors for various applications.

Device study, chemical doping, and logic circuits based on transferred aligned single-walled carbon nanotubes

In this paper, high-performance back-gated carbon nanotube field-effect transistors based on transferred aligned carbon nanotubes were fabricated and studies found that the on/off ratio can reach 107 and the current density can reach 1.6μA∕μm after electrical breakdown. In addition, chemical doping with hydrazine was used to convert the p-type aligned nanotube devices into n-type. These devices were further utilized to demonstrate various logic circuits, including p-type metal-oxide-semiconductor inverters, diode-loaded inverters, complementary metal-oxide-semiconductor inverters, NAND, and NOR gates. This approach could work as the platform for future nanotube-based nanoelectronics.

Scalable Light-Induced Metal to Semiconductor Conversion of Carbon Nanotubes

Coexistence of metallic and semiconducting carbon nanotubes in as-grown samples sets important limits to their application in high-performance electronics. We present the metal-to-semiconductor conversion of carbon nanotubes for field-effect transistors based on both aligned nanotubes and individual nanotube devices. The conversion process is induced by light irradiation, scalable to wafer-size scales and capable of yielding improvements in the channel-current on/off ratio up to 5 orders of magnitude in nanotube-based field-effect transistors. Inactivation of metallic nanotubes in the channels was achieved as a consequence of a diameter-dependent photochemical process that led to a controlled oxidation of the nanotube sidewall and, hence, stronger localization of pi-electrons. Optimization of irradiation conditions yields nearly 90% of depletable nanotube field-effect transistors.

Threshold Voltage and On–Off Ratio Tuning for Multiple-Tube Carbon Nanotube FETs

In this paper, we demonstrate postprocessing techniques to adjust the threshold voltage (Vt) and on-off ratio (ION/IOFF) of multiple-tube carbon nanotube field effect transistors (CNFETs). These postprocessing techniques open up an additional degree of freedom to further tune individual CNFETs in addition to various device synthesis and processing techniques. We demonstrate proof-of-concept experiments and fully characterize their design spaces and tradeoffs. The techniques, threshold voltage setting and on-off ratio tuning, were able to adjust the threshold by as much as 2 V and tune the on-off ratio across 5times103 to times105. In addition,Vt setting could be used as an analysis tool to infer the Vt distribution of grown carbon nanotubes (CNTs). These tuning techniques, combined with processes such as doping, will enable high-performance multiple-nanotube devices.