Nishant Patil

Carbon nanotube computer

The miniaturization of electronic devices has been the principal driving force behind the semiconductor industry, and has brought about major improvements in computational power and energy efficiency. Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy–delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies. Owing to substantial fundamental imperfections inherent in CNTs, however, only very basic circuit blocks have been demonstrated. Here we show how these imperfections can be overcome, and demonstrate the first computer built entirely using CNT-based transistors. The CNT computer runs an operating system that is capable of multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we implement 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This experimental demonstration is the most complex carbon-based electronic system yet realized. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems.

Selective dispersion of high purity semiconducting single-walled carbon nanotubes with regioregular poly(3-alkylthiophene)s

Conjugated polymers, such as polyfluorene and poly(phenylene vinylene), have been used to selectively disperse semiconducting single-walled carbon nanotubes (sc-SWNTs), but these polymers have limited applications in transistors and solar cells. Regioregular poly(3-alkylthiophene)s (rr-P3ATs) are the most widely used materials for organic electronics and have been observed to wrap around SWNTs. However, no sorting of sc-SWNTs has been achieved before. Here we report the application of rr-P3ATs to sort sc-SWNTs. Through rational selection of polymers, solvent and temperature, we achieved highly selective dispersion of sc-SWNTs. Our approach enables direct film preparation after a simple centrifugation step. Using the sorted sc-SWNTs, we fabricate high-performance SWNT network transistors with observed charge-carrier mobility as high as 12 cm(2) V(-1) s(-1) and on/off ratio of >10(6). Our method offers a facile and a scalable route for separating sc-SWNTs and fabrication of electronic devices.

CMOS-Analogous Wafer-Scale Nanotube-on-Insulator Approach for Submicrometer Devices and Integrated Circuits Using Aligned Nanotubes

Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits.

Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections

1D carbon nanotube FET (CNFET)-based circuits offer 4.6times faster FO4 speed and 12times energy-delay product improvement over 32nm node Si CMOS (including diameter and doping variations), provided circuits can be built that are immune to misaligned and metallic nanotubes. A design technique that guarantees correct logic operation in the presence of misaligned nanotubes is also presented.

Circuit-Level Performance Benchmarking and Scalability Analysis of Carbon Nanotube Transistor Circuits

Carbon nanotubes (CNTs) show great promise as extensions to silicon CMOS due to their excellent electronic properties and extremely small size. Using a Carbon Nanotube Field Effect Transistor (CNFET) SPICE model, we evaluate circuit-level performance of CNFET technology in the presence of CNT fabrication-related nonidealities and imperfections, and parasitic resistances and capacitances extracted from the CNFET circuit layout. We use Monte Carlo simulations using the CNFET SPICE model to investigate the effects of three major CNT process-related imperfections on circuit-level performance: 1) doping variations in the CNFET source and drain regions; 2) CNT diameter variations; and 3) variations caused by the removal of metallic CNTs. The simulation results indicate that metallic CNT removal has the most impact on CNFET variation; less than 8% of CNTs grown should be metallic to reduce circuit performance variation. This paper also presents an analytical model for the scalability of CNFET technology. High CNT density (250 CNTs/mum) is critical to ensure that performance (delay and energy) gains over silicon CMOS are maintained or improved with shrinking lithographic dimensions.

Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits

Carbon-nanotube (CNT) field-effect transistors (CNFETs) are promising extensions to silicon CMOS. Simulations show that CNFET inverters fabricated with a perfect CNFET technology have 13 times better energy delay product compared with 32-nm silicon CMOS inverters. The following two fundamental challenges prevent the fabrication of CNFET circuits with the aforementioned advantages: 1) misaligned and mispositioned CNTs and 2) metallic CNTs. Misaligned and mispositioned CNTs can cause incorrect functionality. This paper presents a technique for designing arbitrary logic functions using CNFET circuits that are guaranteed to implement correct functions even in the presence of a large number of misaligned and mispositioned CNTs. Experimental demonstration of misaligned and mispositioned CNT-immune logic structures is also presented.

VMR: VLSI-compatible metallic carbon nanotube removal for imperfection-immune cascaded multi-stage digital logic circuits using Carbon Nanotube FETs

Metallic carbon nanotubes (CNTs) create source-drain shorts in Carbon Nanotube Field Effect Transistors (CNFETs) resulting in excessive leakage (I<inf>on</inf>/I<inf>off</inf> ≪ 5) and highly degraded noise margins. A new technique, VLSI-compatible Metallic-CNT Removal (VMR), overcomes metallic CNT challenges by combining layout design with CNFET processing. VMR produces CNFET circuits with I<inf>on</inf>/I<inf>off</inf> in the range of 10³-10⁵, and overcomes the limitations of existing metallic-CNT removal techniques. VMR enables first experimental demonstration of complex cascaded CNFET logic circuits. Such logic circuits are immune to both mis-positioned and metallic CNTs.

Carbon nanotube circuits in the presence of carbon nanotube density variations

Carbon nanotubes (CNTs) are grown using chemical synthesis. As a result, it is extremely difficult to ensure exact positioning and uniform density of CNTs. Density variations in CNT growth can compromise reliability of carbon nanotube field effect transistor (CNFET) circuits, and result in increased delay variations. A parameterized model for CNT density variations is presented based on experimental data extracted from aligned CNT growth. This model is used to quantify the impact of such variations on design metrics such as noise margin and delay variations of CNFET circuits. Finally, we analyze correlation that exists in aligned CNT growth, and demonstrate how the reliability of CNFET circuits can be significantly improved by taking advantage of such correlation.

Carbon Nanotube Robust Digital VLSI

Carbon nanotube field-effect transistors (CNFETs) are excellent candidates for building highly energy-efficient electronic systems of the future. Fundamental limitations inherent to carbon nanotubes (CNTs) pose major obstacles to the realization of robust CNFET digital very large-scale integration (VLSI): 1) it is nearly impossible to guarantee perfect alignment and positioning of all CNTs despite near-perfect CNT alignment achieved in recent years; 2) CNTs can be metallic or semiconducting depending on chirality; and 3) CNFET circuits can suffer from large performance variations, reduced yield, and increased susceptibility to noise. Todays CNT process improvements alone are inadequate to overcome these challenges. This paper presents an overview of: 1) imperfections and variations inherent to CNTs; 2) design and processing techniques, together with a probabilistic analysis framework, for robust CNFET digital VLSI circuits immune to inherent CNT imperfections and variations; and 3) recent experimental demonstration of CNFET digital circuits that are immune to CNT imperfections. Significant advances in design tools can enable robust and scalable CNFET circuits that overcome the challenges of the CNFET technology while retaining its energy-efficiency benefits.

Solution Assembly of Organized Carbon Nanotube Networks for Thin-Film Transistors

Ultrathin, transparent electronic materials consisting of solution-assembled nanomaterials that are directly integrated as thin-film transistors or conductive sheets may enable many new device structures. Applications ranging from disposable autonomous sensors to flexible, large-area displays and solar cells can dramatically expand the electronics market. With a practical, reliable method for controlling their electronic properties through solution assembly, submonolayer films of aligned single-walled carbon nanotubes (SWNTs) may provide a promising alternative for large-area, flexible electronics. Here, we report SWNT network TFTs (SWNTntTFTs) deposited from solution with controllable topology, on/off ratios averaging greater than 10(5), and an apparent mobility averaging 2 cm(2)/V.s, without any pre- or postprocessing steps. We employ a spin-assembly technique that results in chirality enrichment along with tunable alignment and density of the SWNTs by balancing the hydrodynamic force (spin rate) with the surface interaction force controlled by a chemically functionalized interface. This directed nanoscale assembly results in enriched semiconducting nanotubes yielding excellent TFT characteristics, which is corroborated with mu-Raman spectroscopy. Importantly, insight into the electronic properties of these SWNT networks as a function of topology is obtained.