Alexander I. Krymski

A high speed, 500 frames/s, 1024/spl times/1024 CMOS active pixel sensor

The paper presents a high-speed (500 f/s) large-format 1 K/spl times/1 K 8 bit 3.3 V CMOS active pixel sensor (APS) with 1024 ADCs integrated on chip. The sensor achieves an extremely high output data rate of over 500 Mbytes per second and a low power dissipation of 350 mW at the 66 MHz master clock rate. Principal architecture and circuit solutions allowing such a high throughput are discussed along with preliminary results of the chip characterization.

A 1.5-V 550-/spl mu/W 176/spl times/144 autonomous CMOS active pixel image sensor

This paper addresses the development of a micropower 176/spl times/144 CMOS active pixel image sensor that dissipates one to two orders of magnitude less power than current state-of-the-art CMOS image sensors. The chip operates from a 1.5-V voltage source and the power consumption measured for the chip running from an internal 25.2-MHz clock yielding 30 frames per second is about 550 /spl mu/W. This amount enables the sensor to run from a watch battery. In order to achieve design goals, a low-power sensor design methodology is applied throughout the design process from system-level to process-level, while realizing the performance to satisfy the design specification. As an autonomous sensor, it can be operated with only three pads [GND, VDD (1.2-1.7 V), DATAOUT]. The die occupies 4 mm/sup 2/ of silicon.

A high-speed, 240-frames/s, 4.1-Mpixel CMOS sensor

This paper describes a large-format 4-Mpixel (2352/spl times/1728) sensor with on-chip parallel 10-b analog-to-digital converters (ADCs). The chip size is 20/spl times/20 mm with a 7-/spl mu/m pixel pitch. At a 66-MHz master clock rate and 3.3-V operating voltage, it achieves a high frame rate of 240 frames/s delivering 9.75 Gb/s of data with power dissipation of less than 700 mW. The principal architectural features of the sensor are discussed along with the results of sensor characterization.

A 9-V/Lux-s 5000-frames/s 512/spl times/512 CMOS sensor

A high-responsivity 9-V/Lux-s high-speed 5000-frames/s (at full 512/spl times/512 resolution) CMOS active pixel sensor (APS) is presented in this paper. The sensor was designed for a 0.35-/spl mu/m 2P3M CMOS sensor process and utilizes a five-transistor pixel to provide a true parallel shutter. Column-parallel analog-to-digital converter (ADC) architecture yields fast readout from pixels and digitization of the data simultaneously with acquiring a new frame. The chip has a two-row SRAM to store data from the ADC and read previous rows of data out of the chip. There are a total of 16 parallel ports operating up to 90 MHz delivering /spl sim/1.3 Gpixel/s or 13 Gb/s of data at the maximum rate. In conclusion, a comparison between two high-speed digital CMOS sensor architectures, which are a column-parallel APS and a digital pixel sensor (DPS), is conducted.

A 3-pin 1.5 V 550 mW 176 x 144 self-clocked CMOS active pixel image sensor

This paper addresses the development of a micropower 176 x 144 self-clocked CMOS active pixel image sensor that dissipates oneto-two orders of magnitude less power than current state of the art CMOS image sensors. The chip operates from a 1.5 V voltage source and the power consumption measured for the chip running from an internal 25.2 MHz clock yielding 30 frames per second is about 550 μW. This amount enables the sensor to be run from a watch battery. It is believed that this chip is the world’s lowest power image sensor and the first image sensor designed for a watch battery operation. The camera-on-a-chip operates as a selfclocked 3-pin sensor (GND, VDD (1.2 1.7 V), and DATAOUT). The die occupies 4 mm of silicon.