Eric R. Fossum

A high speed, 500 frames/s, 1024/spl times/1024 CMOS active pixel sensor

The paper presents a high-speed (500 f/s) large-format 1 K/spl times/1 K 8 bit 3.3 V CMOS active pixel sensor (APS) with 1024 ADCs integrated on chip. The sensor achieves an extremely high output data rate of over 500 Mbytes per second and a low power dissipation of 350 mW at the 66 MHz master clock rate. Principal architecture and circuit solutions allowing such a high throughput are discussed along with preliminary results of the chip characterization.

A 1.5-V 550-/spl mu/W 176/spl times/144 autonomous CMOS active pixel image sensor

This paper addresses the development of a micropower 176/spl times/144 CMOS active pixel image sensor that dissipates one to two orders of magnitude less power than current state-of-the-art CMOS image sensors. The chip operates from a 1.5-V voltage source and the power consumption measured for the chip running from an internal 25.2-MHz clock yielding 30 frames per second is about 550 /spl mu/W. This amount enables the sensor to run from a watch battery. In order to achieve design goals, a low-power sensor design methodology is applied throughout the design process from system-level to process-level, while realizing the performance to satisfy the design specification. As an autonomous sensor, it can be operated with only three pads [GND, VDD (1.2-1.7 V), DATAOUT]. The die occupies 4 mm/sup 2/ of silicon.

A high-speed, 240-frames/s, 4.1-Mpixel CMOS sensor

This paper describes a large-format 4-Mpixel (2352/spl times/1728) sensor with on-chip parallel 10-b analog-to-digital converters (ADCs). The chip size is 20/spl times/20 mm with a 7-/spl mu/m pixel pitch. At a 66-MHz master clock rate and 3.3-V operating voltage, it achieves a high frame rate of 240 frames/s delivering 9.75 Gb/s of data with power dissipation of less than 700 mW. The principal architectural features of the sensor are discussed along with the results of sensor characterization.

Foreword special issue on solid-state image sensors

ON ELECTRON DEVICES on solid-state image sensors. We seem to be on a six-year cycle as the previous issues were published in August 1985, May 1991, and October 1997. As reflected by these papers, during the past six years the focus of image sensor R&D has shifted from charge-coupled devices (CCDs) to CMOS image sensors. While it is only an inaccurate indicator of R&D activity, the number of CMOS image sensor papers rose from 13 in the 1997 issue to 26 in this issue, and the number of CCD papers dropped from 16 to five. CCDs continue to dominate the world’s shipment of image sensors in both volume and revenue due to their maturity, concomitant image capture quality and momentum, despite some premature predictions to the contrary (made by myself, I admit). On the other hand, CMOS image sensors have made enormous progress in the same time period with image capture quality now approaching or exceeding CCDs with the additional benefits of reduced power and high levels of “camera-on-a-chip” integration, and are predominate in lower-end image-capture systems and many mobile platforms. Just as the emergence of the consumer camcorder resulted in rapid CCD evolution and improvement in the 1980s, the image sensor business seems about to go through a second phase of rapid growth. This resurgence will be fueled by new applications in mobile personal products, automotive, security, biometrics, and medicine. Most forecasts call for a cross-over point from CCDs to CMOS in shipment volume starting in the next few years. Time will tell if these predictions hold water. This special issue contains papers discussing improvements in pixel photoelectric conversion, dark current, noise and pixel operation. Reduced power dissipation and alternate readout architectures are also presented. Several papers address very-highspeed sensors. Smart sensors with on-chip functions for target tracking, range finding and other nonvisual applications are re-

Detector Arrays for Digital Holographic Storage Applications

This chapter discusses detectors for holographic data storage applications. While it may be possible to use a single detector or linear array of detectors, the focus here is on 2-D arrays of pixels. There are many considerations for the detector array when designing a complete system that arise from the intimate relationship between the holographic storage system, optical readout technique, and the sensor pixels. The chapter begins with a discussion of these considerations, based on the assumption that commercially viable digital holographic data storage (DHDS) systems must be “smaller than a breadbox,” be affordable, have data capacities in the hundreds of gigabytes arena, and have readout rates in the regime of hundreds of megabytes per second. Today there are two primary technology choices for realization of the sensor array: charge-coupled devices (CCDs) and CMOS (complementary metal-oxide-semiconductor) active pixel sensors (APS). Both will be introduced and their relative merits presented [1–6]. In fact the CMOS APS, a much newer technology, will be shown to offer significant advantages over its predecessor, the CCD, when applied to digital holographic data storage systems. An example of a recently-fabricated CMOS APS for use in a DHDS is shown in Fig. 1.

Radiation-induced dark signal in 0.5-μm CMOS APS image sensors

A CMOS APS image sensor test chip, which was designed employing the physical design techniques of enclosed geometry and guard rings and fabricated in a 0.5-micrometers CMOS process, underwent a Co60 (gamma) -ray irradiation experiment. The experiment demonstrated that implementing the physical design techniques of enclosed geometry and guard rings in CMOS APS image sensors is possible. It verified that employing these design techniques does not represent a fundamental impediment for the functionality and performance of CMOS APS image sensors. It further proved that CMOS APS image sensors that employ these physical design techniques yield better dark signal performance in ionizing radiation environment than their counterpart that do not employ those physical design techniques. For one of the different pixel designs that were included in the test chip pixel array, the pre- radiation average dark signal was approximately 1.92 mV/s. At the highest total ionizing radiation dose level used in the experiment (approximately 88 Krad(Si)), average dark signal increased to approximately 36.35 mV/s. After annealing for 168 hours at 100 degree(s)C, it dropped to approximately 3.87 mV/s.