Barmak Mansoorian

A high speed, 500 frames/s, 1024/spl times/1024 CMOS active pixel sensor

The paper presents a high-speed (500 f/s) large-format 1 K/spl times/1 K 8 bit 3.3 V CMOS active pixel sensor (APS) with 1024 ADCs integrated on chip. The sensor achieves an extremely high output data rate of over 500 Mbytes per second and a low power dissipation of 350 mW at the 66 MHz master clock rate. Principal architecture and circuit solutions allowing such a high throughput are discussed along with preliminary results of the chip characterization.

Digital free-space optical interconnections: a comparison of transmitter technologies

We investigate the performance of free-space optical interconnection systems at the technology level. Specifically, three optical transmitter technologies, lead-lanthanum-zirconate-titanate and multiple-quantum-well modulators and vertical-cavity surface-emitting lasers, are evaluated. System performance is measured in terms of the achievable areal data throughput and the energy required per transmitted bit. It is shown that lead-lanthanum-zirconate-titanate modulator and vertical-cavity surface-emitting laser technologies are well suited for applications in which a large fan-out per transmitter is required but the total number of transmitters is relatively small. Multiple-quantum-well modulators, however, are good candidates for applications in which many transmitters with a limited fan-out are needed.

A Low Phase Noise 10GHz Optoelectronic RF Oscillator Implemented Using CMOS Photonics

A mostly integrated 10.2GHz optoelectronic oscillator (OEO) using Si photonics monolithic integration technology is reported. The OEO is a chip-scale device manufactured using a standard 0.13mum SOI CMOS process, with phase noise of -112dBc/Hz at 10kHz carrier offset and RF power consumption of less than 800mW.

Diode-biased AC-coupled ECL-to-CMOS interface circuit

A full CMOS emitter-coupled logic (ECL)-to-CMOS voltage level converter has been developed. A diode-biased AC-coupled circuit is used to convert digital signals from ECL to CMOS voltage levels for use in digital data transmission. This technique makes the receiver insensitive to variations in input signal noise and offset voltage with no substantial penalties in conversion delay. The circuit can be used to retrofit all-CMOS systems to a bipolar ECL environment and to benefit from the reduction of chip-to-chip delays using small-signal transmission-line networks. >