Alexander Platz

Multi‐Scale Mechanical Probing Techniques To Investigate The Stability Of BEOL Layer Stacks With Sub‐100 nm Structures

The stress levels induced by chip‐package interaction (CPI) impose an increased risk of mechanical failure on advanced backend‐of‐line (BEOL) layer stacks in microelectronic circuits if they contain fragile ultralow‐k (ULK) interlayer dielectric (ILD) films. On the one hand, multilevel finite element modeling is used to assess the potential risk at an early stage of the development of new microelectronic products. On the other hand, the theoretical models need as accurate as possible materials parameters as an input to provide realistic results. Moreover, it is highly desirable to have multi‐scale experimental probes available which can provide complementary data to support the modeling calculations. The present paper provides an overview about various mechanical probing techniques which operate on the scale of less than 100 nm up to more than 100 μm. In this way, typical feature sizes are covered which occur from the package level via solder bumps or copper pillars down to small Cu/ULK interconnect struc...

CPI assessment using a novel characterization technique based on bump-assisted scratch-indentation testing

Integration of compliant and brittle ultralow-k (ULK) interlayer dielectric (ILD) materials in advanced backend-of-line (BEOL) layer stacks requires a careful characterization of the mechanical stability of the BEOL stack to assure reliability during chip packaging and under field condition. We present a novel experimental technique which applies normal and shear forces on Cu pillars to test the stability of BEOL layer stacks beneath individual pillars. Critical forces and displacements are recorded with high sensitivity. The test directly verifies if the BEOL withstands the applied stress levels or if mechanical failure occurs.

The effect of polyimide surface treatment on flip-chip assembly

This paper studied the effects of polyimide surface morphology and RIE treatment for lead-free C4 bumping of SOI device on assembly process by flip-chip technique. The characterizations were experimentally carried out with FTIR, AFM and CSAM. The process sequences have been optimized based on the DOE results.