Alexandra Abbadie

Chromium(VI)-free Defect Etching Solutions for Application on Engineered Silicon Substrates

For the last few decades the performance of silicon integrated circuits has steadily progressed, as anticipated by Moore’s Law, primarily through scaling of all critical device dimensions. However, the trend of scaling is slowing down and will finally come to a halt as the scale approaches atomic dimensions. Therefore, innovations other than simple scaling have become the main contributors to better performance. Even the most fundamental material of all, the silicon wafer, is giving way to a variety of engineered substrates, like silicon-oninsulator (SOI) and strained silicon-on-insulator (sSOI).