Eric Neyret

Defect detection on SOI wafers using laser scattering tools

Laser scattering tools are used in production monitoring of wafer defectivity. We present SOI wafer specific behavior related to the intrinsic limitations of laser scattering defect detection. An empiric model of accessible thresholds regarding layer thickness is proposed. When removing roughness induced haze on an SOI structure, the haze level of SOI wafers is clearly linked with structure reflectivity. Since the haze varies in the reverse order of the reflectivity, the defect measurement threshold needs to be adapted to avoid reflectivity induced false counts in wafer characterization. Wafer uniformity must also be considered when choosing the measurement threshold, especially in the case of very thin silicon layers, typically targeted for fully depleted applications. For these advanced applications the laser used in detection tools will have to move to UV light in order to reach detection limits under 0.16 /spl mu/m as required by ITRS roadmaps.

Unibond(R) SOI wafers for ultra-thin films applications

The benefits of Silicon-on-Insulator (SOI) as a substrate material for applications such as high end logic, microprocessors, and low power low voltage devices for portable applications became apparent at the 0.18 /spl mu/m IC generation. Higher speed. lower power and higher packing density for an overall lower manufacturing cost outweigh a higher SOI material cost. New SOI-based IC generations require low silicon thicknesses with very good uniformities. This paper deals with a thickness monitoring strategy in SOI volume production as well as Smart-Cut(R) process developments dedicated to those thin film products.

High Temperature RTP Application in SOI Manufacturing

Significant performance enhancements are offered by silicon on insulator (SOI) or strained silicon, SOI being adopted for advanced devices in sustaining Moore’s law. Sub-45 nm device options are including fully depleted (FD) devices, that are stressing even more specifications for thickness uniformity. Nano-uniformity, considering thickness variation contributions from device level to wafer scale, has been introduced in substrate optimization and latest Unibond products are verifying FD requirements. Rapid Thermal Processing (RTP) based surface smoothing has been introduced in Unibond processing to combine thickness control and product quality requirements.

Smart Cut/spl trade/ transfer of 300 mm [110] and (100) Si layers for hybrid orientation technology

In hybrid-orientation technology (HOT), devices are fabricated on hybrid substrate with [110] and (100) orientations to achieve significant PMOS performance enhancement. Smart cut process is an important step in the substrate engineering for HOT. We investigate the details of layer transfer in the substrates of different orientations and presents the characteristics of product [110] SOI wafers. For the first time, we show that H platelet distributions, splitting kinetics and evolution of post-split surface morphology demonstrate strong substrate orientation dependence. Certain modifications of critical process steps in generic smart cut process flow are required to fabricate high quality [110] SOI wafers.