Alexandre Giulietti

Memory power reduction for the highspeed implementation of turbo codes

Turbo codes achieve the highest coding gain known and should be the best candidates for error correction in high-speed wireless systems. However, the standard implementation of their decoding standard of their decoding algorithm suffers from a large latency and high power consumption making them improper for mobile interactive systems. To overcome this drawback, we systematically analyzed the maximum a posteriori algorithm, the key-building block of the decoder, and stated that memory accesses are the bottleneck. Therefore, we have systematically optimized the data transfer and storage. This paper presents the main results of this optimization, especially those concerning the memory organization and architecture. This optimization reduces the latency by a factor of 600 and the energy per bit by a factor of 20, allowing turbo codes application in future high-speed mobile systems.

Design Methodology: The Strategic Plan

The excellent coding performance make a Turbo codec a desirable component of a communication system, striving the channel limits. Additionally, one wants to see reliable Turbo codec implementations, achieving a high rate, featuring a large degree of flexibility, and last but not least consuming minimum power. In order to face such a huge implementation challenge, we need a strategic plan: a rigorous design methodology.

Mastering the Interleaver

Interleaving has been largely adopted in communication systems as an effective way to spread adjacent symbols in transmission making them independent of the adjacent symbols in reception. In the case of fading channels adjacent symbols are normally affected by fading levels that are highly correlated, generating the so-called burst errors. In order to perform a good detection of the received symbols such bursts should be broken, spreading errors throughout the whole block. This task is performed by the channel interleaver.

Demystifying the Fang-Buda Algorithm

After the breakthrough caused by the introduction of Convolutional Turbo Codes (CTCs) by Berrou and Glavieux [1], extensive consolidation work has led to the publication by Joachim Hagenauer of the so-called Turbo Principle [2] The latter actually generalize the principle underlying Berrou’s Turbo Codes to the decoding of any kind of concatenated error correcting code. In 1994, one year after Berrou’s landmark paper, Pyndiah proposed to decode iteratively Forney Jr.’s Block Product Codes [3, 4], as introduced in Chapter 1 of this book as Serially Concatenated Block Codes or Block Turbo Codes (BTCs).

T@MPO Codec

After having presented the main points to be tackled when implementing turbo coding schemes, in this last Chapter the implementation of a convolutional turbo-codec ASIC is presented, combining the MAP SISO architecture presented in Chapter 3 with collision-free interleaving (Chapter 5) through a design methodology aiming notably at optimizing data transfer and storage (Chapter 2). The low-power, high-speed integrated circuit (T@MPO, Turbo @ Minimum Power) was conceived as a proof of the fact that turbo codes could be used in embedded systems with data rates up to 100 Mbps, still keeping low energy consumption. Sections 6.2 and 6.3 present aspects of the design: design flow and final architecture respectively. Sections 6.4 and 6.5 present results obtained after synthesis and after measurements respectively, describing the test-bed using for obtaining the real coding gain and power consumption figures of the ASIC. Results on the scalability of the architecture proposed in Chapter 3 show that throughputs up to 1 Gbps if possible when other constraints as power consumption and area are traded-off against speed (Section 6.6). The complete set of the ASIC features is finally presented in Section 6.7.

Conquering the Map

A thorough analysis of convolutional turbo codes requires the well-understanding of its decoding algorithm. Two options are normally considered: the Maximum A Posteriori (MAP) algorithm published by Bahl et al. in 1974 [1] and the soft-output Viterbi decoding algorithm [2]. The complete derivation of the MAP is presented, making clear some points that are not thoroughly described in the available literature. Some simplifications normally applied to the MAP algorithm are also seen. Those simplifications are made in order to allow the efficient implementation of MAP decoders as the SISO modules required in convolutional turbo decoding. Trade-offs that have to be tackled when designing turbo decoders are made clear when a complete understanding of the decoding algorithm is achieved; that is the main purpose of Sections 3.2 and 3.3. Section 3.4 deals with different termination schemes for the turbo encoder, pointing out that termination is normally costly from the implementation point of view. Section 3.5 introduces the main bottlenecks when dealing with the log-max MAP algorithm and details several optimization steps that transform the slow recursion inherent to the MAP in a full parallel architecture with a special memory organization targeted at saving energy consumption.