Alexandros C. Dimopoulos

Comparison of Block Matching and Differential Methods for Motion Analysis of the Carotid Artery Wall From Ultrasound Images

Motion of the carotid artery wall is important for the quantification of arterial elasticity and contractility and can be estimated with a number of techniques. In this paper, a framework for quantitative evaluation of motion analysis techniques from B-mode ultrasound images is introduced. Six synthetic sequences were produced using 1) a real image corrupted by Gaussian and speckle noise of 25 and 15 dB, and 2) the ultrasound simulation package Field II. In both cases, a mathematical model was used, which simulated the motion of the arterial wall layers and the surrounding tissue, in the radial and longitudinal directions. The performance of four techniques, namely optical flow (OFHS), weighted least-squares optical flow (OFLK(WLS)), block matching (BM), and affine block motion model (ABMM), was investigated in the context of this framework. The average warping indices were lowest for OFLK(WLS) (1.75 pixels), slightly higher for ABMM (2.01 pixels), and highest for BM (6.57 pixels) and OFHS (11.57 pixels). Due to its superior performance, OFLK(WLS) was used to quantify motion of selected regions of the arterial wall in real ultrasound image sequences of the carotid artery. Preliminary results indicate that OFLK(WLS) is promising, because it efficiently quantified radial, longitudinal, and shear strains in healthy adults and diseased subjects.

Parallel Hardware Stochastic Context-Free Parsers

In this paper a platform is presented, that given a stochastic context-free grammar (SCFG), automatically outputs the description of the parser in synthesizable hardware description language (HDL) which can be downloaded in an Field Programmable Gate Arrays (FPGA) board. Initially, according to our methodology the SCFG is augmented with attributes which store the probability values and can be evaluated through corresponding stack actions. The architecture of the produced system is based on a proposed extension of Earley’s parallel algorithm, which given an input string, generates the parse trees in the form of an AND-Or parse tree. This AND-or parse tree is then traversed using a proposed tree traversal technique in order to execute the corresponding actions in the correct order, so as to compute the necessary probabilities. The platform is suitable for embedded systems applications where a natural language interface is required or in pattern recognition tasks. The parser generated by the presented platfo...

A platform for the automatic generation of attribute evaluation hardware systems

Attribute grammars (AG) allow the addition of context-sensitive properties into context free grammars, augmenting their expressional capabilities by using syntactic and semantic notations, making them in this way a really useful tool for a considerable number of applications. AGs have extensively been utilized in applications such as artificial intelligence, structural pattern recognition, compiler construction and even text editing. Obviously, the performance of an attribute evaluation system resides in the efficiency of the syntactic and semantic subsystems. In this paper, a hardware architecture for an attribute evaluation system is presented, which is based on an efficient combinatorial implementation of Earleys parallel parsing algorithm for the syntax part of the attribute grammar. The semantic part is managed by a special purpose module that traverses the parse tree and evaluates the attributes based on a proposed stack-based approach. The entire system is described in Verilog HDL (hardware design language), in a template form that given the specification of an arbitrary attribute grammar, the HDL synthesizable source code of the system is produced on the fly by a proposed automated tool. The generated code has been simulated for validation, synthesized and tested on an Xilinx FPGA (field programmable gate arrays) board for various AGs. Our method increases the performance up to three orders of magnitude compared to previous approaches, depending on the implementation, the size of the grammar and the input string length. This makes it particularly appealing for applications where attribute evaluation is a crucial aspect, like in real-time and embedded systems. Specifically, a natural language interface is presented, based on a question-answering application from the area of airline flights.

An efficient hardware implementation for AI applications

A hardware architecture is presented, which accelerates the per- formance of intelligent applications that are based on logic programming. The logic programs are mapped on hardware and more precisely on FPGAs (Field Programmable Gate Array). Since logic programs may easily be transformed into an equivalent Attribute Grammar (AG), the underlying model of implementing an embedded system for the aforementioned applications can be that of an AG evaluator. Previous attempts to the same problem were based on the use of two separate components. An FPGA was used for mapping the inference engine and a conventional RISC microprocessor for mapping the unification mechanism and user defined additional semantics. In this paper a new architecture is presented, in order to drastically reduce the number of the required processing elements by a factor of n (length of input string). This fact and the fact of using, for the inference engine, an extension of the most efficient parsing algorithm, allowed us to use only one component i.e. a single FPGA board, eliminating the need for an additional external RISC microprocessor, since we have embedded two “PicoBlaze” Soft Processors into the FPGA. The proposed architecture is suitable for embedded system applications where low cost, portability and low power consumption is of crucial importance. Our approach was tested with numerous examples in order to establish the performance improvement over previous attempts.

Embedded intelligence in smart cities through multi-core smart building architectures: Research achievements and challenges

Economic growth in Europe has been, strongly associated with urbanization, overwhelming cities with vehicles. This renders mobility inside cities problematic, since it is often associated with large waste of time in traffie congestions, environmental pollution and accidents. Cities struggle to invent and deploy “smart” solutions in the domain of urban mobility, so as to offer innovative services to citizens and visitors and improve the overall quality of life. In this context, the paper discusses on the fundamental challenges that cities face when trying to become smarter, focusing on the particular area of smart buildings and the management of multi-core, smart building architectures and presents some key research achievements and relevant research challenges.

Hardware Natural Language Interface

In this paper an efficient architecture for natural language processing is presented, implemented in hardware using FPGAs (Field Programmable Gate Arrays). The system can receive sentences belonging to a subset of Natural Languages (NL) from the internet or as SMS (Short Message Service). The recognition task of the input string uses Earley’s parallel parsing algorithm and produces intermediate code according to the semantics of the grammar. The intermediate code can be transmitted to a computer, for further processing. The high computational cost of the parsing task in conjunction with a possible large amount of input sentences, to be processed simultaneously, justify the hardware implementation of the grammar (syntax and semantics). An extensive illustrative example is given from the area of question answering, in order to show the feasibility of the proposed system.

A Formal Method for Rapid SoC Prototyping

In this paper a formal method is proposed, based on Attribute Grammars (AG), for rapid SoC prototyping. A generic platform is also proposed for the automatic SoC implementation of AG-based applications. The proposed system, given the specification of the application in the formalism of Attribute Grammars, automatically produces the necessary hardware modules for the syntactic and semantic analysis of input strings belonging to that grammar. The produced implementation tackles with the recognition task of the input string, using a hardware implementation of an extension of Earleys parallel parsing algorithm. Moreover, the system exhibits capabilities of inexactness. The attribute evaluation makes usage of a stack-based hardware. The hardware modules are described in Verilog Hardware Description Language (Verilog HDL) and synthesizedin a Xilinx Virtex-5 ML506 FPGA. For the illustration of the proposed system, an example from the area of hardware compilers is given.

The role of autonomous aggregators in IoT multi-core systems

The Internet of Things constitutes a prominent field, integrating smart devices and people into complex systems that may vary in scale. To ensure the constant availability and performance of provided services, alternative distributed architectures should be explored, promoting system scalability. To this end, alternative architectures for the IoT are proposed. Commonly an intermediate layer consisting of aggregators, controlling sensors and actuators and providing a service interface to IoT applications, is incorporated in such architectures. To promote scalability of IoT systems, aggrerators should to operate as autonomous entities. For an aggregator to become autonomous, self-management policies should be enforced. In the paper, we discuss autonomous aggregator software, running on multi-core IoT systems to efficiently implement such policies. A demonstrator for smart buildings, developed as a proof of concept for the proposed concepts, is also presented.

Hardware Inexact Grammar Parser

In this paper, a platform is presented, that given a Stochastic Context-Free Grammar (SCFG), automatically outputs the description of a parser in synthesizable Hardware Description Language (HDL) which can be downloaded in an FPGA (Field Programmable Gate Arrays) board. Although the proposed methodology can be used for various inexact models, the probabilistic model is analyzed in detail and the extension to other inexact schemes is described. Context-Free Grammars (CFG) are augmented with attributes which represent the probability values. Initially, a methodology is proposed based on the fact that the probabilities can be evaluated concurrently with the parsing during the parse table construction by extending the fundamental parsing operation proposed by Chiang & Fu. Using this extended operation, an efficient architecture is presented based on Earley’s parallel algorithm, which given an input string, generates the parse table while evaluating concurrently the probabilities of the generated dotted gramma...

TELIOS: A Tool for the Automatic Generation of Logic Programming Machines

In this paper the tool TELIOS is presented, for the automatic generation of a hardware machine, corresponding to a given logic program. The machine is implemented using an FPGA, where a corresponding inference machine, in application specific hardware, is created on the FPGA, based on a BNF parser, to carry out the inference mechanism. The unification mechanism is based on actions embedded between the non-terminal symbols and implemented using special modules on the FPGA.