Ioannis Panagopoulos

Behavioral synthesis with systemC

Having to cope with the continuously increasing complexity of modern digital systems, hardware designers are considering more and more seriously language based methodologies for parts of their designs. Last year the introduction of a new language for hardware descriptions, the SystemC C++ class library, initiated a closer relationship between software and hardware descriptions and development tools. This paper presents a synthesis environment and the corresponding synthesis methodology, based on traditional compiler generation techniques, which incorporate SystemC, VHDL and Verilog to transform existing algorithmic software models into hardware system implementations. Following this approach, reusability of software components is introduced in the hardware world and time-to-market is decreased, as shown by experimental results.

An Embedded Microprocessor for Intelligent Control

Abstract The conventional approach for the implementation of the knowledge base of a planning agent, on an intelligent embedded system, is solely of software nature. It requires the existence of a compiler that transforms the initial declarative logic program, specifying the knowledge base, to its equivalent procedural one, to be programmed to the embedded system’s microprocessor. This practice increases the complexity of the final implementation (the declarative to sequential transformation adds a great amount of software code for simulating the declarative execution) and reduces the overall system’s performance (logic derivations require the use of a stack and a great number of jump instructions for their evaluation). The design of specialized hardware implementations, which are only capable of supporting logic programs, in an effort to resolve the aforementioned problems, introduces limitations in their use in applications where logic programs need to be intertwined with traditional procedural ones in a desired application. In this paper, we exploit HW/SW codesign methods to present a microprocessor, capable of supporting hybrid applications using both programming approaches. We take advantage of the close relationship between attribute grammar (AG) evaluation and knowledge engineering methods to present a programmable hardware parser that performs logic derivations and combine it with an extension of a conventional RISC microprocessor that performs the unification process to report the success or failure of logic derivations. The extended RISC microprocessor is still capable of executing conventional procedural programs, thus hybrid applications can be implemented. The presented implementation increases the performance of logic derivations for the control inference process (experimental analysis yields an approximate 1000% – 10 times increase in performance) and reduces the complexity of the final implemented code through the introduction of an extended C language called C-AG that simplifies the programming of hybrid procedural-declarative applications.

An efficient hardware implementation for AI applications

A hardware architecture is presented, which accelerates the per- formance of intelligent applications that are based on logic programming. The logic programs are mapped on hardware and more precisely on FPGAs (Field Programmable Gate Array). Since logic programs may easily be transformed into an equivalent Attribute Grammar (AG), the underlying model of implementing an embedded system for the aforementioned applications can be that of an AG evaluator. Previous attempts to the same problem were based on the use of two separate components. An FPGA was used for mapping the inference engine and a conventional RISC microprocessor for mapping the unification mechanism and user defined additional semantics. In this paper a new architecture is presented, in order to drastically reduce the number of the required processing elements by a factor of n (length of input string). This fact and the fact of using, for the inference engine, an extension of the most efficient parsing algorithm, allowed us to use only one component i.e. a single FPGA board, eliminating the need for an additional external RISC microprocessor, since we have embedded two “PicoBlaze” Soft Processors into the FPGA. The proposed architecture is suitable for embedded system applications where low cost, portability and low power consumption is of crucial importance. Our approach was tested with numerous examples in order to establish the performance improvement over previous attempts.

Knowledge Representation Using a Modified Earley’s Algorithm

Attribute grammars (AGs) have been proven to be valuable tools in knowledge engineering applications. In this paper, we formalize knowledge representation problems in their AG equivalent form and we extend the Earley’s parsing algorithm in order to evaluate simultaneously attributes based on semantic rules related to logic programming. Although Earley’s algorithm can not be extended to handle attribute evaluation computations for all possible AGs, we show that the form of AGs created for equivalent logic programs and the related attribute evaluation rules are such that allow their use for knowledge representation. Hence, a fast one-pass left to right AG evaluator is presented that can effectively be used for logic programs. We also suggest a possible software/hardware implementation for the proposed approach based on existing hardware parsers for Earley’s algorithm, which work in coordination with a conventional RISC microprocessor and can assist in the creation of small-scale applications on intelligent embedded systems with optimized performance.

A hardware extension of the RISC microprocessor for Attribute Grammar evaluation

Conventional implementations of Attribute Grammar (AG) evaluators in embedded systems today, are solely of software nature. A compiler transforms the parsers specification along with the declarative attribute evaluation rules into a behaviorally equivalent procedural program to be executed on the microprocessor. This approach affects the final systems performance as well as the complexity of the final implementation. Efforts in presenting hardware implementations of AG evaluators, although efficient enough in terms of performance, are usually fully implemented in hardware and as a consequence restricted to a single application. We exploit HW/SW codesign methods in the effort of presenting a hardware implementation of AG evaluators that is both reprogrammable and increases the desired systems performance. We achieve that by extending a conventional RISC microprocessor by combining it with a programmable implementation of a hardware parser to propose a fully programmable AG evaluator that supports the execution of hybrid combinations of declarative-procedural code. The hardware parser increases design efficiency of tree derivations while the RISC microprocessor handles the attribute evaluation computations. As a result, performance is increased while design flexibility required in embedded system applications is preserved.

A top-down interactive behavioral synthesis environment

Behavioral synthesis of digital circuits offers an effective way to deal with the increasing complexity of hardware design. Even though it has been the subject of considerable research efforts over the last twenty years, practical implementations have not been widely accepted by industry yet. This happens due to the fact that designers demand interaction, which allows them to submit different constraints (especially with respect to interface specifications) and obtain optimal results while exploring all applicable implementation conditions. This paper presents a new, GUI enhanced and grammar based, interactive synthesis environment. The underlying methodology allows designers to supplement behavioral synthesis optimizations with constraints among the operators in the textual algorithmic description, to meet their implementation preferences. Consequently, it raises the feasibility for high-level design space exploration by supporting better user control of automated synthesis results.