Christos Pavlatos

An Embedded Microprocessor for Intelligent Control

Abstract The conventional approach for the implementation of the knowledge base of a planning agent, on an intelligent embedded system, is solely of software nature. It requires the existence of a compiler that transforms the initial declarative logic program, specifying the knowledge base, to its equivalent procedural one, to be programmed to the embedded system’s microprocessor. This practice increases the complexity of the final implementation (the declarative to sequential transformation adds a great amount of software code for simulating the declarative execution) and reduces the overall system’s performance (logic derivations require the use of a stack and a great number of jump instructions for their evaluation). The design of specialized hardware implementations, which are only capable of supporting logic programs, in an effort to resolve the aforementioned problems, introduces limitations in their use in applications where logic programs need to be intertwined with traditional procedural ones in a desired application. In this paper, we exploit HW/SW codesign methods to present a microprocessor, capable of supporting hybrid applications using both programming approaches. We take advantage of the close relationship between attribute grammar (AG) evaluation and knowledge engineering methods to present a programmable hardware parser that performs logic derivations and combine it with an extension of a conventional RISC microprocessor that performs the unification process to report the success or failure of logic derivations. The extended RISC microprocessor is still capable of executing conventional procedural programs, thus hybrid applications can be implemented. The presented implementation increases the performance of logic derivations for the control inference process (experimental analysis yields an approximate 1000% – 10 times increase in performance) and reduces the complexity of the final implemented code through the introduction of an extended C language called C-AG that simplifies the programming of hybrid procedural-declarative applications.

Parallel Hardware Stochastic Context-Free Parsers

In this paper a platform is presented, that given a stochastic context-free grammar (SCFG), automatically outputs the description of the parser in synthesizable hardware description language (HDL) which can be downloaded in an Field Programmable Gate Arrays (FPGA) board. Initially, according to our methodology the SCFG is augmented with attributes which store the probability values and can be evaluated through corresponding stack actions. The architecture of the produced system is based on a proposed extension of Earley’s parallel algorithm, which given an input string, generates the parse trees in the form of an AND-Or parse tree. This AND-or parse tree is then traversed using a proposed tree traversal technique in order to execute the corresponding actions in the correct order, so as to compute the necessary probabilities. The platform is suitable for embedded systems applications where a natural language interface is required or in pattern recognition tasks. The parser generated by the presented platfo...

A platform for the automatic generation of attribute evaluation hardware systems

Attribute grammars (AG) allow the addition of context-sensitive properties into context free grammars, augmenting their expressional capabilities by using syntactic and semantic notations, making them in this way a really useful tool for a considerable number of applications. AGs have extensively been utilized in applications such as artificial intelligence, structural pattern recognition, compiler construction and even text editing. Obviously, the performance of an attribute evaluation system resides in the efficiency of the syntactic and semantic subsystems. In this paper, a hardware architecture for an attribute evaluation system is presented, which is based on an efficient combinatorial implementation of Earleys parallel parsing algorithm for the syntax part of the attribute grammar. The semantic part is managed by a special purpose module that traverses the parse tree and evaluates the attributes based on a proposed stack-based approach. The entire system is described in Verilog HDL (hardware design language), in a template form that given the specification of an arbitrary attribute grammar, the HDL synthesizable source code of the system is produced on the fly by a proposed automated tool. The generated code has been simulated for validation, synthesized and tested on an Xilinx FPGA (field programmable gate arrays) board for various AGs. Our method increases the performance up to three orders of magnitude compared to previous approaches, depending on the implementation, the size of the grammar and the input string length. This makes it particularly appealing for applications where attribute evaluation is a crucial aspect, like in real-time and embedded systems. Specifically, a natural language interface is presented, based on a question-answering application from the area of airline flights.

An efficient hardware implementation for AI applications

A hardware architecture is presented, which accelerates the per- formance of intelligent applications that are based on logic programming. The logic programs are mapped on hardware and more precisely on FPGAs (Field Programmable Gate Array). Since logic programs may easily be transformed into an equivalent Attribute Grammar (AG), the underlying model of implementing an embedded system for the aforementioned applications can be that of an AG evaluator. Previous attempts to the same problem were based on the use of two separate components. An FPGA was used for mapping the inference engine and a conventional RISC microprocessor for mapping the unification mechanism and user defined additional semantics. In this paper a new architecture is presented, in order to drastically reduce the number of the required processing elements by a factor of n (length of input string). This fact and the fact of using, for the inference engine, an extension of the most efficient parsing algorithm, allowed us to use only one component i.e. a single FPGA board, eliminating the need for an additional external RISC microprocessor, since we have embedded two “PicoBlaze” Soft Processors into the FPGA. The proposed architecture is suitable for embedded system applications where low cost, portability and low power consumption is of crucial importance. Our approach was tested with numerous examples in order to establish the performance improvement over previous attempts.

Hardware Natural Language Interface

In this paper an efficient architecture for natural language processing is presented, implemented in hardware using FPGAs (Field Programmable Gate Arrays). The system can receive sentences belonging to a subset of Natural Languages (NL) from the internet or as SMS (Short Message Service). The recognition task of the input string uses Earley’s parallel parsing algorithm and produces intermediate code according to the semantics of the grammar. The intermediate code can be transmitted to a computer, for further processing. The high computational cost of the parsing task in conjunction with a possible large amount of input sentences, to be processed simultaneously, justify the hardware implementation of the grammar (syntax and semantics). An extensive illustrative example is given from the area of question answering, in order to show the feasibility of the proposed system.

A Formal Method for Rapid SoC Prototyping

In this paper a formal method is proposed, based on Attribute Grammars (AG), for rapid SoC prototyping. A generic platform is also proposed for the automatic SoC implementation of AG-based applications. The proposed system, given the specification of the application in the formalism of Attribute Grammars, automatically produces the necessary hardware modules for the syntactic and semantic analysis of input strings belonging to that grammar. The produced implementation tackles with the recognition task of the input string, using a hardware implementation of an extension of Earleys parallel parsing algorithm. Moreover, the system exhibits capabilities of inexactness. The attribute evaluation makes usage of a stack-based hardware. The hardware modules are described in Verilog Hardware Description Language (Verilog HDL) and synthesizedin a Xilinx Virtex-5 ML506 FPGA. For the illustration of the proposed system, an example from the area of hardware compilers is given.

Hardware Inexact Grammar Parser

In this paper, a platform is presented, that given a Stochastic Context-Free Grammar (SCFG), automatically outputs the description of a parser in synthesizable Hardware Description Language (HDL) which can be downloaded in an FPGA (Field Programmable Gate Arrays) board. Although the proposed methodology can be used for various inexact models, the probabilistic model is analyzed in detail and the extension to other inexact schemes is described. Context-Free Grammars (CFG) are augmented with attributes which represent the probability values. Initially, a methodology is proposed based on the fact that the probabilities can be evaluated concurrently with the parsing during the parse table construction by extending the fundamental parsing operation proposed by Chiang & Fu. Using this extended operation, an efficient architecture is presented based on Earley’s parallel algorithm, which given an input string, generates the parse table while evaluating concurrently the probabilities of the generated dotted gramma...

TELIOS: A Tool for the Automatic Generation of Logic Programming Machines

In this paper the tool TELIOS is presented, for the automatic generation of a hardware machine, corresponding to a given logic program. The machine is implemented using an FPGA, where a corresponding inference machine, in application specific hardware, is created on the FPGA, based on a BNF parser, to carry out the inference mechanism. The unification mechanism is based on actions embedded between the non-terminal symbols and implemented using special modules on the FPGA.

Hardware Embedded System on a Chip for the Normal ECG Recognition

This paper proposes a highly efficient embedded system, implemented entirely in reconfigurable hardware, for the extraction of electrocardiogram (ECG) measurement parameters and the recognition of the normal ECG. The entire process takes place on an FPGA and is based on the syntactic pattern recognition approach. The underling model for this system is that of Attribute Grammars (AG), whose descriptive power allows the concurrent recognition and measurement of the input ECG. The proposed generic platform for syntactic pattern recognition applications, is using the fastest parallel Context Free Grammar parsing algorithm in the bibliography.

Knowledge Representation Using a Modified Earley’s Algorithm

Attribute grammars (AGs) have been proven to be valuable tools in knowledge engineering applications. In this paper, we formalize knowledge representation problems in their AG equivalent form and we extend the Earley’s parsing algorithm in order to evaluate simultaneously attributes based on semantic rules related to logic programming. Although Earley’s algorithm can not be extended to handle attribute evaluation computations for all possible AGs, we show that the form of AGs created for equivalent logic programs and the related attribute evaluation rules are such that allow their use for knowledge representation. Hence, a fast one-pass left to right AG evaluator is presented that can effectively be used for logic programs. We also suggest a possible software/hardware implementation for the proposed approach based on existing hardware parsers for Earley’s algorithm, which work in coordination with a conventional RISC microprocessor and can assist in the creation of small-scale applications on intelligent embedded systems with optimized performance.