Alexey Lopich

A SIMD Cellular Processor Array Vision Chip With Asynchronous Processing Capabilities

This paper describes an architecture and implementation of a digital vision chip that features mixed asynchronous/synchronous processing techniques. The vision chip is based on a massively parallel cellular array of processing elements, which incorporate a photo-sensor with an ADC and digital processing circuit, consisting of 64 bits of local memory, ALU, flag register and communication units. The architecture has two modes of operation: synchronous SIMD mode for low-level image processing based on local pixel data, and continuous-time mode for global operations. Additionally, the periphery circuits enable asynchronous address extraction, fixed pattern addressing and flexible, random access data I/O. A 19 × 22 proof-of-concept array has been manufactured in 0.35 μm CMOS technology. The chip delivers 15.6 GOPS for binary and 1 GOPS for grayscale operations dissipating 26.4 mW, while operating at 2.5 V and 75 MHz clock. Experimental measurements indicate that the presented concept favorably compares with other digital and analog vision chips. The results of low- and medium-level image processing on the chip are presented.

Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing

This paper describes a new architecture for a cellular processor array integrated circuit, which operates in both discrete- and continuous-time domains. Asynchronous propagation networks, enabling trigger-wave operations, distance transform calculation, and long-distance inter-processor communication, are embedded in an SIMD processor array. The proposed approach results in an architecture that is efficient in implementing both local and global image processing algorithms

Asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array

In this paper we present an implementation of an asynchronous cellular processor array that facilitates binary trigger-wave propagations, extensively used in various image processing algorithms. The circuit operates in a continuous-time mode, achieving high operational performance and low power consumption. A 24 times 60 proof-of-concept array integrated circuit has been fabricated in a 0.35 mum 3-metal CMOS process and tested. Occupying only 16 times 8 mum2 the binary wave-propagation cell is used as a coprocessor in a general-purpose processor-per-pixel array that is designed for focal-plane image processing. The results of global operations such as object reconstruction and hole filling are presented.

ASPA: Focal Plane digital processor array with asynchronous processing capabilities

In this paper we present implementation and experimental results for a digital vision chip that operates in mixed asynchronous/synchronous mode. Mixed configuration benefits from full programmability (discrete-time mode) and high operational performance in global image processing operations (continuous-time mode) thus extending the application field of smart sensors from low- to medium-level processing. A 19x22 proof-of-concept chip was fabricated and tested. At peak operational frequency (150 MHz) each cell provides 9.6 MOPS thus achieving area utilization 820.8 MOPS/mm2 and power efficiency 29 GOPS/W.

A Control System for a Cellular Processor Array

Presented in this paper is a system that controls the SCAMP-3 cellular processor array vision chip, and provides an interface between it and a host system. This system can be used in real-time image processing, or computer vision applications. The system includes a sequencer for issuing instructions to the array processor, a configurable analogue interface and read-out circuitry, a system controller, which enables system operation and communication with the host, and a suite of software components, which include libraries, simulator, compiler and user interface. The presented hardware is a stand-alone vision system, which can be used in the development of PC-based or embedded applications

Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing

This paper presents an FPGA realisation of an application-specific cellular processor array designed for asynchronous skeletonization of binary images. The skeletonization algorithm is based on iterative thinning utilizing a ‘grassfire’ transformation approach. The purpose of this work was to test the performance of a fully parallel asynchronous processor array and to evaluate the inhomogeneity of wave propagation velocity. A proof-of-concept design has been implemented and evaluated, the results are presented and discussed.

A general-purpose vision processor with 160×80 pixel-parallel SIMD processor array

In this paper we present a vision processor, which incorporates a 160×80 SIMD array of pixel-processors. The processor operates with a 100MHz clock and 1.8V supply. The device provides 640 GOPS (binary) and 23 GOPS (greyscale) consuming 0.5 W. The chip occupies 50mm2 and is fabricated in a standard 0.18 μm CMOS process. The I/O interface supports 200 MPixels/s (greyscale), 1.6 GPixels/s (binary) and 40 MPixels/s (address-event readout) data rate, and PE-parallel image sensing mode for embedded high-speed vision applications. Experimental results indicate that the performance of the presented chip approaches the efficiency of recently reported application-specific vision processors, while providing full programmability and thus being adjustable to a wide range of applications.

Implementation of an asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array

In this paper we present an implementation of an asynchronous cellular processor array that facilitates binary trigger-wave propagations, extensively used in various image processing algorithms. The circuit operates in a continuous-time mode, achieving high operational performance and low power consumption. A 24 times 60 proof-of-concept array integrated circuit has been fabricated in a 0.35 mum 3-metal CMOS process and tested. Occupying only 16 times 8 mum2 the binary wave-propagation cell is used as a coprocessor in a general-purpose processor-per-pixel array that is designed for focal-plane image processing. The results of global operations such as object reconstruction and hole filling are presented.

An 80×80 general-purpose digital vision chip in 0.18μm CMOS technology

In this paper we present an implementation of the asynchronous/synchronous processor array (ASPA2) — a digital SIMD vision chip. The chip has been fabricated in a 0.18 μm CMOS process and comprises 80×80 array of pixel processors. The architecture of the chip is overviewed, the design of the processing cell is presented and implementation issues are discussed. At 75 MHz ASPA2 demonstrates 373 GOPS/W power and 871 MOPS/mm area efficiency, making it suitable for the design of high speed and low power vision systems.

A processor element for a mixed signal cellular processor array vision chip

A combined analogue and digital processing element for a pixel-parallel vision chip has been designed in 0.18µm CMOS technology. In addition to 7 analogue registers, each pixel incorporates 14 bits of digital memory. In the analogue domain its processing capabilities include addition, subtraction and squaring, with digital domain NOT and OR operators also available. The processing element has dimensions of 32×32µm and is designed to operate at 10MHz. A test chip has been fabricated.